• 제목/요약/키워드: Ag paste bump

검색결과 8건 처리시간 0.018초

Ag Paste bump 구조를 갖는 인쇄회로기판의 Ag migration 발생 안전성 평가 (Investigation of Ag Migration from Ag Paste Bump in Printed Circuit Board)

  • 송철호;김영훈;이상민;목지수;양용석
    • 한국재료학회지
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    • 제20권1호
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    • pp.19-24
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    • 2010
  • The current study examined Ag migration from the Ag paste bump in the SABiT technology-applied PCB. A series of experiments were performed to measure the existence/non-existence of Ag in the insulating prepreg region. The average grain size of Ag paste was 30 nm according to X-ray diffraction (XRD) measurement. Conventional XRD showed limitations in finding a small amount of Ag in the prepreg region. The surface morphology and cross section view in the Cu line-Ag paste bump-Cu line structure were observed using a field emission scanning electron microscope (FE-SEM). The amount of Ag as a function of distance from the edge of Ag paste bump was obtained by FE-SEM with energy dispersive spectroscopy (EDS). We used an electron probe micro analyzer (EPMA) to improve the detecting resolution of Ag content and achieved the Ag distribution function as a function of the distance from the edge of the Ag paste bump. The same method with EPMA was applied for Cu filled via instead of Ag paste bump. We compared the distribution function of Ag and Cu, obtained from EPMA, and concluded that there was no considerable Ag migration effect for the SABiT technology-applied printed circuit board (PCB).

SABiT 공법적용 인쇄회로기판의 은 페이스트 범프 크기 및 제작 조건에 따른 전기 저항 특성 (Characterization of Electrical Resistance for SABiT Technology-Applied PCB : Dependence of Bump Size and Fabrication Condition)

  • 송철호;김영훈;이상민;목지수;양용석
    • 한국전기전자재료학회논문지
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    • 제23권4호
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    • pp.298-302
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    • 2010
  • We investigated the resistance change behavior of SABiT (Samsung Advanced Bump interconnection Technology) technology-applied PCB (Printed Circuit Board) with the various bump sizes and fabrication conditions. Many testing samples with different bump size, prepreg thickness, number of print on the formation of Ag paste bump, were made. The resistance of Ag paste bump itself was calculated from the Ag paste resistivity and bump size, measured by using 4-point probe method and FE-SEM (Field Emission Scanning Electron Microscope), respectively. The contact resistance between Ag paste bump and conducting Cu line were obtained by subtracting the Cu line and bump resistances from the measured total resistance. It was found that the contact resistance drastically changed with the variation of Ag paste bump size and the contact resistance had the largest influence on total resistance. We found that the bump size and contact resistance obeyed the power law relationship. The resistance of a circuit in PCB can be estimated from this kind of relationship as the bump size and fabrication technique vary.

Au 스터드 범프 본딩과 Ag 페이스트 본딩으로 연결된 소자의 온도 측정 및 접촉 저항에 관한 연구 (Temperature Measurement and Contact Resistance of Au Stud Bump Bonding and Ag Paste Bonding with Thermal Heater Device)

  • 김득한;유세훈;이창우;이택영
    • 마이크로전자및패키징학회지
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    • 제17권2호
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    • pp.55-61
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    • 2010
  • 탄탈륨실리사이드 히터가 내장된 소자를 Ag 페이스트와 Au SBB(Stud Bump Bonding)를 이용하여 Au가 코팅 된 기판에 각각 접합 하였다. 전단 테스트와 전류를 흐르면서 열 성능을 측정하였다. Au 스터드 범프 본딩의 최적 플립칩 접합조건은 전단 후 파괴면 관찰하여 설정하였으며, 기판 온도를 $350^{\circ}C$, 소자 온도를 $250^{\circ}C$에서 하중을 300 g/bump 로 하여 접합하는 경우가 최적 조건이였다. 히터에 5 W 인가시 소자의 온도는 Ag 페이스트를 이용한 접합의 경우 최대 온도는 약 $50^{\circ}C$이었으며, Au 금속층을 갖고 있는 실리콘 기판에 Au 스터드 본딩으로 접합된 인 경우 약 $64^{\circ}C$를 나타내었다. 기판과의 접촉면적이 와이어본딩과 Au 스터드 범프 본딩 가 약 300배가 차이가 나는 경우 약 $14^{\circ}C$ 차이를 나타내었고, 전사모사를 통하여 접합면의 접촉저항이 중요한 이유임을 알 수 있었다.

Optimization of Material and Process for Fine Pitch LVSoP Technology

  • Eom, Yong-Sung;Son, Ji-Hye;Bae, Hyun-Cheol;Choi, Kwang-Seong;Choi, Heung-Soap
    • ETRI Journal
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    • 제35권4호
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    • pp.625-631
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    • 2013
  • For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

나노 첨가제에 따른 Sn-Ag-Cu계 솔더페이스트의 젖음성 및 금속간화합물 (Wettability and Intermetallic Compounds of Sn-Ag-Cu-based Solder Pastes with Addition of Nano-additives)

  • 서성민;스리 하리니 라젠드란;정재필
    • 마이크로전자및패키징학회지
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    • 제29권1호
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    • pp.35-41
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    • 2022
  • 5G 시대를 맞아, 인공지능, 클라우드 컴퓨팅, 자율주행 차량, 스마트 제조 등의 기술 소요가 증가하고 있다. 전자기기의 고효율을 위해 고집적회로 및 패키징 연구는 중요하다. 전해도금된 솔더는 범프 조성의 균일성에 한계가 있다. 작은 크기의 솔더 파우더로 구성된 솔더 페이스트는 고집적 패키징에 일반적으로 사용되는 솔더 중 하나이다. 솔더 페이스트에 나노 입자를 첨가하거나 기판 표면 마감 처리를 하여 젖음성을 향상시키고, 금속 패드 계면에서 금속간화합물의 성장을 억제하는 연구가 진행중이다. 본 논문은 나노 입자 첨가를 통한 솔더 페이스트의 젖음성 향상과 계면 금속간화합물의 성장을 억제하는 원리에 대하여 설명한다.

Novel Low-Volume Solder-on-Pad Process for Fine Pitch Cu Pillar Bump Interconnection

  • Bae, Hyun-Cheol;Lee, Haksun;Eom, Yong-Sung;Choi, Kwang-Seong
    • 마이크로전자및패키징학회지
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    • 제22권2호
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    • pp.55-59
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    • 2015
  • Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.

Fine-Pitch Solder on Pad Process for Microbump Interconnection

  • Bae, Hyun-Cheol;Lee, Haksun;Choi, Kwang-Seong;Eom, Yong-Sung
    • ETRI Journal
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    • 제35권6호
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    • pp.1152-1155
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    • 2013
  • A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

무연솔더 접합부의 미세조직 특성 (Microstructural Charicteristics of Pb-free Solder Joints)

  • 유아미;장재원;김목순;이종현;김준기
    • 대한용접접합학회:학술대회논문집
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    • 대한용접접합학회 2010년도 춘계학술발표대회 초록집
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    • pp.82-82
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    • 2010
  • 표면실장 공법을 통해 CSP 패키지를 보드에 실장 하는데 있어 무연솔더 접합부의 신뢰성에 영향을 미치는 인자 중 가장 중요한 것은 접합부에 형성되는 IMC (Intermetallic compound, 금속간화합물)인 것으로 알려져 있다. 접합부의 칩 부분에는 솔더와 칩의 UBM (Under bump metalization)이 접합하여 IMC가 형성되나, 보드 부분에는 솔더와 보드의 UBM 뿐만 아니라 그 사이에 솔더 페이스트가 함께 접합되어 IMC가 형성된다. 본 연구에서는 패키지의 신뢰성 연구를 위해 솔더 페이스트의 유무 및 두께에 따른 무연 솔더 접합부의 미세조직의 변화를 분석하였다. 본 실험에서는 Sn-3.0(Wt.%)Ag-0.5Cu 조성과 본 연구진에 의해 개발된 Sn-Ag-Cu-In 조성의 직경 $450{\mu}m$ 솔더 볼을 사용하였으며, 솔더 페이스트는 상용 Sn-3.0Ag-0.5Cu (ALPHA OM-325)를 사용하였다. 칩은 ENIG (Electroless nickel immersion gold) finish pad가 형성된 CSP (Chip scale package)를, 보드는 OSP (Organic solderability preservative)/Cu finish pad가 형성된 것을 사용하였다. 실험 방법은 보드를 솔더 페이스트 없이 플라즈마 처리 한 것, 솔더 페이스트를 $30{\mu}m$ 두께로 인쇄한 것, $120{\mu}m$의 두께로 인쇄한 것, 이렇게 3가지 조건으로 준비한 후, 솔더 볼이 bumping된 칩을 mounting하여, $242^{\circ}C$의 peak 온도 조건의 oven(1809UL, Heller)에서 reflow를 실시하여 패키지를 형성하였다. 이후 시편은 정밀 연마한 후, OM(Optical Microscopic)과 SEM(scanning electron microscope) 및 EDS(energy dispersive spectroscope)를 사용하여 솔더 접합부 IMC의 미세조직을 관찰, 분석하였다.

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