• Korean Journal of Materials Research
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• v.20 no.1
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• pp.19-24
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• 2010

The current study examined Ag migration from the Ag paste bump in the SABiT technology-applied PCB. A series of experiments were performed to measure the existence/non-existence of Ag in the insulating prepreg region. The average grain size of Ag paste was 30 nm according to X-ray diffraction (XRD) measurement. Conventional XRD showed limitations in finding a small amount of Ag in the prepreg region. The surface morphology and cross section view in the Cu line-Ag paste bump-Cu line structure were observed using a field emission scanning electron microscope (FE-SEM). The amount of Ag as a function of distance from the edge of Ag paste bump was obtained by FE-SEM with energy dispersive spectroscopy (EDS). We used an electron probe micro analyzer (EPMA) to improve the detecting resolution of Ag content and achieved the Ag distribution function as a function of the distance from the edge of the Ag paste bump. The same method with EPMA was applied for Cu filled via instead of Ag paste bump. We compared the distribution function of Ag and Cu, obtained from EPMA, and concluded that there was no considerable Ag migration effect for the SABiT technology-applied printed circuit board (PCB).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.298-302
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• 2010

We investigated the resistance change behavior of SABiT (Samsung Advanced Bump interconnection Technology) technology-applied PCB (Printed Circuit Board) with the various bump sizes and fabrication conditions. Many testing samples with different bump size, prepreg thickness, number of print on the formation of Ag paste bump, were made. The resistance of Ag paste bump itself was calculated from the Ag paste resistivity and bump size, measured by using 4-point probe method and FE-SEM (Field Emission Scanning Electron Microscope), respectively. The contact resistance between Ag paste bump and conducting Cu line were obtained by subtracting the Cu line and bump resistances from the measured total resistance. It was found that the contact resistance drastically changed with the variation of Ag paste bump size and the contact resistance had the largest influence on total resistance. We found that the bump size and contact resistance obeyed the power law relationship. The resistance of a circuit in PCB can be estimated from this kind of relationship as the bump size and fabrication technique vary.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.2
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• pp.55-61
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• 2010

The device with tantalum silicide heater were bonded by Ag paste and Au SBB(Stud Bump Bonding) onto the Au coated substrate. The shear test after Au ABB and the thermal performance under current stressing were measured. The optimum condition of Au SBB was determined by fractured surface after die shear test and $350^{\circ}C$ for substrate, $250^{\circ}C$ for die during flip chip bonding with bonding load of about 300 g/bump. With applying 5W through heater on the device, the maximum temperature with Ag paste bonding was about $50^{\circ}C$. That with Au SBB on Au coated Si substrate showed $64^{\circ}C$. The difference of maximum temperatures is only $14^{\circ}C$, even though the difference of contact area between Ag paste bonding and Au SBB is by about 300 times and the simulation showed that the contact resistance might be one of the reasons.

• ETRI Journal
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• v.35 no.4
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.1
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• pp.35-41
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• 2022

In the era of Fifth-Generation (5G), technology requirements such as Artificial Intelligence (AI), Cloud computing, automatic vehicles, and smart manufacturing are increasing. For high efficiency of electronic devices, research on high-intensity circuits and packaging for miniaturized electronic components is important. A solder paste which consists of small solder powders is one of common solder for high density packaging, whereas an electroplated solder has limitation of uniformity of bump composition. Researches are underway to improve wettability through the addition of nanoparticles into a solder paste or the surface finish of a substrate, and to suppress the formation of IMC growth at the metal pad interface. This paper describes the principles of improving the wettability of solder paste and suppressing interfacial IMC growth by addition of nanoparticles.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.55-59
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• 2015

Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.

• ETRI Journal
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• v.35 no.6
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.82-82
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• 2010

표면실장 공법을 통해 CSP 패키지를 보드에 실장 하는데 있어 무연솔더 접합부의 신뢰성에 영향을 미치는 인자 중 가장 중요한 것은 접합부에 형성되는 IMC (Intermetallic compound, 금속간화합물)인 것으로 알려져 있다. 접합부의 칩 부분에는 솔더와 칩의 UBM (Under bump metalization)이 접합하여 IMC가 형성되나, 보드 부분에는 솔더와 보드의 UBM 뿐만 아니라 그 사이에 솔더 페이스트가 함께 접합되어 IMC가 형성된다. 본 연구에서는 패키지의 신뢰성 연구를 위해 솔더 페이스트의 유무 및 두께에 따른 무연 솔더 접합부의 미세조직의 변화를 분석하였다. 본 실험에서는 Sn-3.0(Wt.%)Ag-0.5Cu 조성과 본 연구진에 의해 개발된 Sn-Ag-Cu-In 조성의 직경 $450{\mu}m$ 솔더 볼을 사용하였으며, 솔더 페이스트는 상용 Sn-3.0Ag-0.5Cu (ALPHA OM-325)를 사용하였다. 칩은 ENIG (Electroless nickel immersion gold) finish pad가 형성된 CSP (Chip scale package)를, 보드는 OSP (Organic solderability preservative)/Cu finish pad가 형성된 것을 사용하였다. 실험 방법은 보드를 솔더 페이스트 없이 플라즈마 처리 한 것, 솔더 페이스트를 $30{\mu}m$ 두께로 인쇄한 것, $120{\mu}m$의 두께로 인쇄한 것, 이렇게 3가지 조건으로 준비한 후, 솔더 볼이 bumping된 칩을 mounting하여, $242^{\circ}C$의 peak 온도 조건의 oven(1809UL, Heller)에서 reflow를 실시하여 패키지를 형성하였다. 이후 시편은 정밀 연마한 후, OM(Optical Microscopic)과 SEM(scanning electron microscope) 및 EDS(energy dispersive spectroscope)를 사용하여 솔더 접합부 IMC의 미세조직을 관찰, 분석하였다.