• 한국전자통신학회논문지
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• 제7권1호
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• pp.15-20
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• 2012

본 논문에서는 디지털 마이크로파 통신 시스템 수신기의 동작범위(Dynamic Range) 향상을 위한 설계 방법을 K-band FEM(Front-End Module)에 적용하여 설계 및 분석하였다. 동작범위를 광범위하게 설계하기 위해 저 잡음 증폭기(LNA)의 잡음지수를 최소화하여 증폭된 입력신호 레벨을 최소화하는 방법을 제안하였으며, 주파수 변환은 높은 선택도(Q)와 안정도가 높은 위상고정 유전체 발진기(PL-DRO) 및 변환이득을 가지는 능동믹서로 구성하였다. 각각의 모듈을 집적화하여 측정한 결과 약 54dB의 변환이득(CG)과 1.3dB의 전제 잡음지수(NF)를 나타내었다.

• ETRI Journal
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• 제42권6호
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• 수산해양기술연구
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• 제56권1호
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• pp.71-81
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• 2020

This paper proposes a possibility of using active front-end rectifier with the SVPWM method for induction motor speed control, which is applicable to small electric propulsion boats. The proposed method can produce a more precise sinusoidal input current waveform and a higher power factor than conventional methods. Its speed, torque, input current, DC voltage, and load current control performance are similar to or better than those of conventional methods. Through computer simulations using the PSIM program, the validity of the proposed method was verified by comparing and analyzing the characteristics of the conventional methods and the proposed method.

• 전기학회논문지
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• 제57권7호
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• pp.1235-1240
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• 2008

In this paper, we presented an active RFID system in 2.45GHz range including LNA, Mixer and gain block. And in this work, a link budget model for RFID applications are proposed. We describe the detailed design and implementation of our system. Our components in RFID system has features such as low Noise Figure, reliable energy budget, and standard compliance with ISO 18000-4. Our receiver is effective for development and evaluation of prototype applications because of the flexibility of the design hardware. So, our platform will be suitable for versatile item management applications.

• Journal of Power Electronics
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• 제12권2호
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• pp.276-284
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• 2012

AC/AC power conversion is widely used to feed AC loads with a variable voltage and/or a variable frequency from a constant voltage constant frequency power grid or to connect critical loads to an unreliable power supply while delivering a very balanced and accurate sinusoidal voltage system of constant amplitude and frequency. The load specifications will clearly impose the requirements for the inverter stage of the power converter, while wider ranges of choices are available for the rectifier. This paper investigates the utilization of a buck-type current source rectifier as the active front-end stage of an AC/AC converter for applications that require an adjustable DC-link voltage as well as elimination of the low-frequency common mode voltage. The proposed solution is to utilize a combination of two or more zero current vectors in the Space Vector Modulation (SVM) technique for Current Sources Rectifiers (CSR).

• 전기학회논문지P
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• 제52권4호
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• pp.148-153
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• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.435-436
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• 2017

This papaer is study on thermal analysis of the active-front-end(AFE) rectifier for solid-state-transformer(SST) applications. finite element analysis simulation model is combined by switching component model, power diode and heat-sink model. thermal model is calculated by computer program and feedback the result. using simulation result analysis switching loss and compare to thermal diffusion of the heat in the model for steady-state operation.

• 해양환경안전학회지
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• 제25권4호
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• pp.498-503
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• 2019

해양산업분야에서는 극심한 대기오염으로 인하여 전기추진선박에 대한 관심이 높아지고 있다. 이로 인해 선내 전력품질의 저하를 개선하기 위한 연구가 활발히 진행되고 있다. 기존 DFE 정류기의 입력전류 고조파 함유량을 완화시키기 위해 수동형필터, 노치필터, 능동형필터 등을 이용한 다양한 방법이 등장하였다. 그 중에서도 능동필터의 일종인 AFE(Active Front End) 정류장치가 우수한 기술로써 평가받고 있다. 본 논문에서는 공간벡터변조에 의한 AFE정류장치의 전류제어방식을 제안하였다. 기존의 히스테리시스 방식, 삼각파 변조방식 및 공간벡터변조방식을 PSIM을 사용해 시뮬레이션을 수행하여 비교, 분석하였고, 그 결과 공간벡터변조방식이 구조가 간단하고 성능이 가장 우수함을 확인하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 추계학술대회
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• pp.62-64
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• 2018

In two-stage single-phase inverters, inherent double line frequency component is present at both input and output of the front-end converter. Generally large electrolytic capacitors are required to eliminate the ripple. It is well known that the low frequency ripple shortens the lifespan of the capacitor hence the system reliability. However, the ripple can hardly be eliminated without the hardware combined with an energy storage device or a certain control algorithm. In this paper, a novel power-decoupling control method is proposed to eliminate the double line frequency ripple at the front-end converter of the DC/AC power conversion system. The proposed control algorithm is composed of two loop, ripple rejection loop and average voltage control loop and no extra hardware is required. In addition, it does not require any information from the phase-locked-loop (PLL) of the inverter and hence it is independent of the inverter control. In order to prove the validity and feasibility of the proposed algorithm a 5kW Dual Active Bridge DC/DC converter and a single-phase inverter are implemented, and experimental results are presented.

• 전자공학회논문지
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• 제53권10호
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• pp.34-39
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• 2016

본 논문에서는 체내 이식용 신경 신호 기록 장치를 위한 저전압 저전력 아날로그 front-end 집적회로를 설계하였다. 제안된 집적 회로는 1 Hz에서 5 kHz 주파수 대역에 존재하는 신경 신호를 처리하기 위해 저잡음 neural 증폭기와 대역폭 조절이 가능한 능동 bandpass 필터로 구성되어 있다. Neural 증폭기는 우수한 잡음 특성을 위해 source-degenerated folded-cascode 연산증폭기를 기반으로 하여 설계하였고, 능동 필터의 경우 저전력의 current-mirror 연산증폭기를 이용하여 설계하였다. 능동 필터의 high-pass cutoff 주파수는 1 Hz에서 300 Hz까지 제어가 가능하며, low-pass cutoff 주파수는 300 Hz에서 8 kHz까지 제어가 가능하다. 전체 아날로그 front-end 회로는 53.1 dB의 전압 이득 성능과 1 Hz에서 10 kHz 대역에 대해서 $4.68{\mu}Vrms$의 입력 잡음 성능과 3.67의 noise efficiency factor 성능을 보인다. $18-{\mu}m$ CMOS 공정을 이용하여 설계를 하였고 1-V 전원에서 $3.2{\mu}W$의 전력 소모 성능을 갖는다. 칩 레이아웃 면적은 $0.19 mm^2$ 이다.