• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.8
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• pp.744-751
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• 2004

This paper presents the implementation of the low cost and high speed RF ATE(Automatic Test Equipment) system, which can be a reasonable solution for reducing the test cost of RF devices. This paper suggests high speed and precise measurement capabilities which are realized by the 16 independent RF ports with high speed switching time and high accuracy digitizer using the industry standard Versus module eXtensions for Instrument(VXI) General Purpose Interface Bus(GPIB) interfaces. Also, the system has the capabilities of quad-site test which can dramatically increase the device throughput. This paper concludes with the demonstration of the implemented ATE system through the setup of RF Power Amplifier Module(PAM), which is under the most competitive market situation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.5
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• pp.51-56
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• 2020

Measurement accuracy and required time is important to make ATE(Automatic test equipment) system in Ka band, and SCPI commands of power meter which is a representative RF test equipment are studied in this paper. Comparison data between FETCH and MEASURE which are SCPI commands are measured in 30 G ~ 31 GHz and -70 ~ +20 dBm using two power sensor. The data show that FETCH which is the fastest SCPI is able to get reliable data in linear interval above noise level. MEASURE which is the best accurate command takes longer time than FETCH, and the longest time is 13.2 seconds. These results offer that measurement accuracy and required time of the two SCPI for power meter and would be used as a guideline for efficient ATE system in Ka band.

• ETRI Journal
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• v.37 no.4
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• Journal of Information Processing Systems
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• v.4 no.4
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• pp.121-132
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• 2008

VLSI chips have been tested using various automatic test equipment (ATE). Although each ATE has a similar structure, the language for ATE is proprietary and it is not easy to convert a test program for use among different ATE vendors. To address this difficulty we propose a tester structure expression language, a tester language with a novel format. The developed language is called the general tester language (GTL). Developing an interpreter for each tester, the GTL program can be directly applied to the ATE without conversion. It is also possible to select a cost-effective ATE from the test program, because the program expresses the required ATE resources, such as pin counts, measurement accuracy, and memory capacity. We describe the prototype environment for the GTL and the tester selection tool. The software size of the prototype is approximately 27,800 steps and 15 manmonths were required. Using the tester selection tool, the number of man-hours required in order to select an ATE could be reduced to 1/10. A GTL program was successfully executed on actual ATE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.74-79
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• 2006

Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-Chip (SoC) adopting Advanced Microcontroller Bus Architecture (AMBA) bus system. Accordingly, this architecture has a deficiency of not being able to concurrently shifting in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. While preserving the compatability with the ARM TIC, since scan in and out operations can be performed simultaneously, test application time through the expensive Automatic Test Equipment (ATE) can be drastically reduced.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.3
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• pp.453-459
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• 2020

It is important to increase the probability that all developed weapon systems can be operated in a steady state at any time. In the case of Integrated Logistics Support, this probability is referred to as operational availability, and the numerical value is quantified during the development process. There are several ways to improve operational availability for successful development of weapon systems. One of the methods is to reduce total corrective maintenance time through Automatic Test Equipment(ATE). Recently, customers in the defense market have become aware of this and demand ways to improve operational availability of weapon systems. Therefore, this paper proposes ways to improve operational availability of weapon systems by changing the method of operating the ATE. The detailed method is to allow field maintenance personnel to carry out field maintenance support onsite. This is an effective way to reduce the total corrective maintenance time of weapon systems by reducing the travel time of field maintenance personnel. The proposed ATE is proved to be able to achieve superior maintenance and operational availability.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.3
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• pp.389-396
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• 2020

In order to obtain a good quality product, a proper verification of production/test facilities must be preceded before the quality conformity inspection of the product. Among the various production/test facilities, ATE is widely used in the civilian industry such as the automotive industry, aerospace industry, semiconductor industry today. In addition, ATE is actively used in the defense industry production and performance tests. This paper is the result of systematically verifying the Design Conformance of ATS which is ATE of military FM radio set using various methods. And It is expected to be a good reference at the present time when the design conformity verification procedure for ATE for military supplies is not documented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.360-360
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• 2010

반도체 산업은 지속적인 design rule 감소로 인해 직접도 및 Pin Count가 점점 증가함에 따라 보증해야할 회로의 수와 기능이 더불어 증가하고 있으며, 그 중 Test Cost 감소 방법 확보가 시급하게 되었다. 이에 따라 Test Cost 감소와 직결된 Test Time 감소 방법이 다양하게 제시되고 연구되고 있다. 본 논문은 Test Time의 한 부분인 반도체 검사 장비 (Automatic Test Equipment)의 효율적인 제어 방법을 제공함으로써, 관련 분야의 이해를 돕고자 한다.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.291-296
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• 2015

This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with $0.18{\mu}m$ Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is $0.514mm^2$.