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http://dx.doi.org/10.3745/JIPS.2008.4.4.121

Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development  

Sato, Masayuki (Genesis Technology Inc., presently Taiyo Yuden Corp.)
Wakamatsu, Hiroki (Genesis Technology Inc., presently Oki Engineering Co.)
Arai, Masayuki (Tokyo Metropolitan University)
Ichino, Kenichi (Tokyo Metropolitan University)
Iwasaki, Kazuhiko (Tokyo Metropolitan University)
Asakawa, Takeshi (Tokai University)
Publication Information
Journal of Information Processing Systems / v.4, no.4, 2008 , pp. 121-132 More about this Journal
Abstract
VLSI chips have been tested using various automatic test equipment (ATE). Although each ATE has a similar structure, the language for ATE is proprietary and it is not easy to convert a test program for use among different ATE vendors. To address this difficulty we propose a tester structure expression language, a tester language with a novel format. The developed language is called the general tester language (GTL). Developing an interpreter for each tester, the GTL program can be directly applied to the ATE without conversion. It is also possible to select a cost-effective ATE from the test program, because the program expresses the required ATE resources, such as pin counts, measurement accuracy, and memory capacity. We describe the prototype environment for the GTL and the tester selection tool. The software size of the prototype is approximately 27,800 steps and 15 manmonths were required. Using the tester selection tool, the number of man-hours required in order to select an ATE could be reduced to 1/10. A GTL program was successfully executed on actual ATE.
Keywords
VLST test; VLSI tester; ATE; tester language; GTL; Tester selection tool;
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