• Journal of the Korea Society of Computer and Information
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• v.12 no.1 s.45
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• pp.253-260
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• 2007

A multimedia converter is used to create media suitable for own environment. If the data complying with own demands can not be created, it may accompany with a problem that has to convert the data with another transcoder. In addition, conventional converters do not consider source QoS and target QoS sufficiently, meaning that users should have a significant knowledge base about various media in order to obtain desired results. These problems become limits on the UMA(Universal Multimedia Access) environment. In this paper, we create a suitable transcoding path before performing the Digital Item conversion in consideration of source QoS and target QoS. The created transcoding path performs the adaptive transcoding using unit exchanges featuring connectivity. The consideration of QoS allows users to use the multimedia easily. Since the proposed model, in addition, use the unit transcoder, it provides a excellent adaptive capability for new QoS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.129-134
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• 2014

This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.414-422
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• 2013

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1435-1444
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• 2008

In this paper, we designed a reduced height waveguide(WG) to microstrip mode converter with a short transition length. The mode converter is composed of a mode converter using E-plane probe and a modified impedance transformer. The mode converter was designed using a probe shorted to top of a 50 ohm ridge WG. The modified impedance transformer was designed to connect the mode converter to the reduced height WG. For wide bandwidth operation, the coupling of the two parts was tuned. The structure of the mode converter was optimized for low loss and wide bandwidth, and the optimized mode converter was fabricated. The performance of the mode converter was extracted using the thru and line S-parameters for back-to-back connections, and the connector loss was calibrated. The mode converter has a right angle structure and short transition length, 7.2 mm. The mode converter shows excellent performances; the insertion loss of 0.12 dB at 15 GHz, and the return loss above 10 dB for the full Ku-band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.19-26
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• 2006

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them compared to the conventional ones. A moebius-band averaging technique is adopted at the proposed ADC to improve performance. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The INL and DNL are within ${\pm}0.5 LSB$, respectively. The active chip occupies an area of $0.28mm^2$ in 0.18um CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1259-1264
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• 1999

In this paper, the High-speed, Low-power Analog-Digital Conversion Archecture is porposed using the Pipelined archecture for High-speed conversion rate and the Successive-Approximation archecture for Low-power consumption. This archecture is the Successive-Approximation archecture using Pipelined Comparator array to change reference voltage during Holding Time. The Analog-to-Digital Converter for video processing is designed using 0.8${\mu}{\textrm}{m}$ CMOS tchnology. When an 6-bit 10MS/s Analog-to-Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 37dB at a sampling rate of 10MHz with 100KHz sine input signal. The power consumption is 1.46mW at 10MS/s. When an 8-bit 10MS/s Analog-to Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41dB at a sampling rate of 100MHz with 100KHz sine input signal. The power consumption is 4.14m W at 10MS/s.

• The Journal of the Acoustical Society of Korea
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• v.17 no.7
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• pp.74-78
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• 1998

본 논문에서는 고속의 변환속도를 갖는 파이프라인드 방식과 저전력 특성을 갖는 축차 비교 방식 구조를 혼용하여 고속, 저전력 아날로그-디지털 변환기를 설계하였다. 제안 된 구조는 축차 비교 방식의 변환에서 비교기를 파이프라인드 구조로 연결하여 홀드된 주기 에 비교기의 기준 전위를 전 비교기의 출력값에 의해 변환하도록 하여 고속 동작이 가능하 도록 하였다. 제안된 구조에 의해 8비트 아날로그 디지털 변환기를 0.8㎛ CMOS공정으로 HSPICE를 이용하여 시뮬레이션한 결과, INL/DNL은 각각 ±0.5/±1이었으며, 100kHz 사인 입력 신호를 10MS/s로 샘플링 하여 DFT측정 결과 SNR은 41dB를 얻을 수 있었다. 10MS/s의 변환 속도에서 전력 소모는 4.14mW로 측정되었다.

• Korean Journal of Optics and Photonics
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• v.14 no.4
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• pp.454-459
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• 2003

We report the first demonstration of 10 Gb/s wavelength conversion in a Mach-Zehnder interferometric wavelength converter monolithically integrated with a loss-coupled DFB probe source. The integrated device is fabricated using a BRS (buried ridge stripe) structure with an undoped InP clad layer on the top of a passive waveguide to reduce high propagation loss. The device exhibited a static extinction ratio of 11 dB. Good performance at 10 Gb/s is obtained with an extinction ratio of 7 dB and a power penalty of 2.8 dB at a 10$^{-9}$ bit error rate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1250-1259
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• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• Journal of Korea Multimedia Society
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• v.10 no.2
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• pp.278-287
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• 2007

Even though a variety of types of multimedia data are being used on the basis of user characteristics and demands, all devices do not always support playing all multimedia data. Accordingly, a multimedia transcoder is used to create media suitable for each environments. This is due to the dissimilarity between the source QoS and the target QoS. Therefore, we need to consider adapting the two dissimilar QoS. Therefore in this paper, we create a suitable application-specific transcoding path with unit transcoders before performing the media transcoding in consideration of source QoS and target QoS. and the created transcoding path performs the transcoding. Here, creating a UTR(Unit Transcoder) conversion path that considers the transcoding possibility and the minimum of the UTR will allow the playback of various multimedia data with convenience. and The consideration of QoS allows users to use the multimedia easily.