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http://dx.doi.org/10.6109/jkiice.2014.18.1.129

A 10-bit 10-MS/s Asynchronous SAR analog-to-digital converter with digital-to-analog converter using MOM capacitor  

Jeong, Yeon-Ho (Department of Electronic Engineering, Kumoh National Institute of Technology)
Jang, Young-Chan (Department of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.18, no.1, 2014 , pp. 129-134 More about this Journal
Abstract
This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.
Keywords
successive approximation; analog-to-digital converter; digital-to-analog converter; metal-oxide-metal(MOM);
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Times Cited By KSCI : 1  (Citation Analysis)
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