• Journal of IKEEE
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• v.14 no.3
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• pp.232-235
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• 2010

A 60GHz active phase shifter with 65nm CMOS is presented by replacing passive switches in switched-line type phase shifter with active ones. Active-switch phase shifter is composed of active-switch blocks and passive delay network blocks. The active-switch phase shifter design is compact compare with the conventional vector-sum phase shifter. Active-switch blocks are designed to accomplish required input and output impedances whose requirements are different whether the switch is on or off. And passive delay network blocks are composed of lumped L,C instead of normal microstrip line to reduce the size of the circuit. An 1-bit phase shifter is fabricated by TSMC 65nm CMOS technology and measurement results present -4dB average insertion loss and 120 degree phase shift at 65GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2006.10a
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• pp.77-77
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• 2006

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1027-1033
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• 2013

In this work, a D-band imaging detector has been developed in a 65-nm CMOS technology for high frequency imaging application. The circuit was designed based on the resistive self-mixing of MOSFET devices. The fabricated detector exhibits a maximum responsivity of 400 V/W and minimum NEP of 100 $pW/Hz^{1/2}$ at 145 GHz. The chip size is $400{\mu}m{\times}450{\mu}m$ including the probing pads and a balun, while the core of the circuit occupies only $150{\mu}m{\times}100{\mu}m$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.393-396
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• 2018

Herein, a 94-GHz low-noise amplifier (LNA) using the 65-nm CMOS process is presented. The LNA is composed of a four-stage differential common-source amplifier and impedance matching is accomplished with transformers. The fabricated LNA chip shows a peak gain of 25 dB at 94 GHz and has a 3-dB bandwidth at 5.5 GHz. The chip consumes 46 mW of DC power from a 1.2-V supply, and the total chip area, including the pads, is $0.3mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.10
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• pp.832-835
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• 2017

In this paper, V-band differential low noise amplifier(LNA) using 65-nm CMOS process for high speed wireless data communication is presented. The LNA is composed of 3-stage common-source differential amplifiers with neutralization of feedback capacitances using MOS capacitors and impedance matching utilizing transformers. The fabricated LNA has a peak gain of 23 dB at 63 GHz and 3 dB bandwidth of 6 GHz. The chip area of LNA is $0.3mm^2$ and the LNA consumes 32 mW DC power from 1.2 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.9
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• pp.915-921
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• 2013

This work presents a 77 GHz low noise amplifier(LNA) for automotive radar systems using 65 nm RF CMOS process. The LNA is composed of three stage common source amplifiers and includes transmission line matching networks. To reduce the time for three dimensional EM simulation, we optimize the transmission line impedance matching network using a pre-built EM library. The proposed compact simulation technique is confirmed by measurement results. The peak gain of the LNA is 10 dB at 77 GHz and input/output return losses are below -10 dB around the design frequency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.05a
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• pp.88-91
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• 1993

In this study 9.5/65/35 PLZT was selected which has the excellent quadratic electro-optic property and slim-loop. It was fabricated by the methods of vacuum hot-pressing and sintering. The electrode of color filter was evaporated using the interdigital type masks. Hysteresis and transmission characteristics were measured. The coercive field and the nontransmited field were correlative. Aging effect was measured according to time at same temperature. Wavelengths of RGB were chosen 700[nm] for red, 545[nm] for green and 435[nm] for blue by the standard of the Commission Internationale del Eclaiage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.5
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• pp.678-681
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• 2020

In this paper, we analyzed the noise figure of cascode low noise amplifier (LNA) based on the measured data of 65nm CMOS devices. By using the channel thermal noise model of transistors, we expanded noise figure equation and divided the equation into three parts to see its contributions to noise figure. We also varied design parameters such as bias point, transistor gate width, and operating frequency. Our results show that different noise sources dominate at the different operating frequencies. One can easily find the noise transition frequency with device models in ahead of the practical design. Therefore, this research provides a low noise design approach for different operating frequencies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.