• 전기학회논문지
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• 제67권6호
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• pp.745-752
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• 2018

ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.

• 한국전자파학회논문지
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• 제25권11호
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• pp.1164-1171
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• 2014

Bulk Current Injection(BCI) 테스트는 전류 주입 프로브를 사용하여 측정하고자 하는 Integrated Circuit(IC)에 전류를 주입하여 Electromagnetic Compatibility(EMC) 규격을 충족시키는지 시험하는 방법이다. 본 논문에서는 국제전기표준회의에서 제정한 IEC 62132-part 3에서 규정하는 BCI 테스트의 전류 주입 프로브를 대체하여, RF 잡음을 인가할 수 있는 마이크로스트립 커플러 구조를 제안하였다. 전통적으로 높은 전원 전압을 사용하는 자동차 IC 테스트에 사용되어 오던 BCI 전류 주입 프로브를 저 전압을 사용하는 저 전력 IC의 테스트에 사용할 수 있는 마이크로스트립 커플러 구조를 개발하여 그 유효성을 100 MHz에서부터 1,000 MHz까지의 주파수 영역에서 비교 및 검증하였다. 또한, 주파수에 따라 전류 주입 프로브를 통한 RF 잡음 인가와 마이크로스트립 커플러 구조를 통한 RF 잡음 인가 시 규정한 노이즈를 얻는데 필요한 전력을 dBm 단위로 측정, 비교하여 마이크로스트립 커플러 구조를 이용한 경우에 더 적은 전력으로 필요한 RF 잡음을 주입할 수 있음을 확인하였다.

• ETRI Journal
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• 제36권6호
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• pp.931-941
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• 2014

Many methodologies for clock mesh networks have been introduced for two-dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three-dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through-silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.

• 한국표면공학회지
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• 제56권3호
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• pp.180-184
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• 2023

Scholars have proposed wafer-level bonding and three-dimensional (3D) stacked integrated circuit (IC) and have investigated Cu-Cu bonding to overcome the limitation of Moore's law. However, information about quantitative Cu-Cu direct-bonding conditions, such as temperature, pressure, and interfacial adhesion energy, is scant. This study determines the optimal temperature and pressure for Cu-Cu bonding by varying the bonding temperature to 100, 150, 200, 250, and 350 ℃ and pressure to 2,303 and 3,087 N/cm². Various conditions and methods for surface treatment were performed to prevent oxidation of the surface of the sample and remove organic compounds in Cu direct bonding as variables of temperature and pressure. EDX experiments were conducted to confirm chemical information on the bonding characteristics between the substrate and Cu to confirm the bonding mechanism between the substrate and Cu. In addition, after the combination with the change of temperature and pressure variables, UTM measurement was performed to investigate the bond force between the substrate and Cu, and it was confirmed that the bond force increased proportionally as the temperature and pressure increased.

• ETRI Journal
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• 제25권1호
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• pp.19-24
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• 2003

This paper describes the performance of a Ku-band 5-bit monolithic phase shifter with metal semiconductor field effect transistor (MESFET) switches and the implementation of a ceramic packaged phase shifter for phase array antennas. Using compensation resistors reduced the insertion loss variation of the phase shifter. Measurement of the 5-bit phase shifter with a monolithic microwave integrated circuit demonstrated a phase error of less than $7.5{\circ}$ root-mean-square (RMS) and an insertion loss variation of less than 0.9 dB RMS for 13 to 15 GHz. For all 32 states of the developed 5-bit phase shifter, the insertion losses were $8.2{\pm}1.4$dB, the input return losses were higher than 7.7 dB, and the output return losses were higher than 6.8 dB for 13 to 15 GHz. The chip size of the 5- bit monolithic phase shifter with a digital circuit for controlling all five bits was 2.35 mm ${\times}$1.65 mm. The packaged phase shifter demonstrated a phase error of less than $11.3{\circ}$ RMS, measured insertion losses of 12.2 ${\pm}$2.2 dB, and an insertion loss variation of 1.0 dB RMS for 13 to 15 GHz. For all 32 states, the input return losses were higher than 5.0 dB and the output return losses were higher than 6.2 dB for 13 to 15 GHz. The size of the packaged phase shifter was 7.20 mm${\times}$ 6.20 mm.

• 한국진공학회지
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• 제14권4호
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• pp.207-214
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• 2005

본 연구에서는 스위치, 위상변위기, 감쇄기등 전파제어회로를 설계 및 제작할 수 있는 pHEMT스위치 소자에 적합한 에피구조를 설계하였다. 고성능의 스위치 소자를 위한 pHEMT 채널층 구조는 이중 면도핑층을 가지며 사용 중 게이트 전극의 전계강도가 약한 깊은 쪽 채널층의 Si 면농도가 상층부보다 약 1/4정도 낮을 경우 격리도등 우수한 특성을 보였다. 설계된 에피구조와 ETRI의 $0.5\mu$m pHEMT MMIC 공정을 이용하여 2.4GHz 및 5GHz 대역 표준 무선랜 단말기에 활용 가능한 SPDT Tx/Rx MMIC 스위치를 설계 및 제작하였다. 제작된 SPDT형 스위치는 주파수 6.0 GHz, 동작전압 0/-3V에서 삽입손실 0.849 dB, 격리도 32.638 dB, 그리고 반사손실 11.006 dB의 특성을 보였으며, 전력전송능력인 $P\_{1dB}$는 약 25dBm, 그리고 선형성의 척도인 IIP3는 42 dBm 이상으로 평가되었다. 이와 같은 칩의 성능은 본 연구에서 개발된 SPDT 단일고주파집적회로 스위치가 2.4GHz뿐만 아니라 SGHB 대역 무선랜 단말기에 활용이 충분히 가능함을 말해준다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.320-330
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• 2012

In this paper, we investigate the power integrity of grid structures for power and ground distribution on printed circuit board (PCB). We propose the 2D transmission line method (TLM)-based model for efficient frequency-dependent impedance characterization and PCB-package-integrated circuit (IC) co-simulation. The model includes an equivalent circuit model of fringing capacitance and probing ports. The accuracy of the proposed grid model is verified with test structure measurements and 3D electromagnetic (EM) simulations. If the grid structures replace the plane structures in PCBs, they should provide effective shielding of the electromagnetic interference in mobile systems. An analytical model to predict the shielding effectiveness (SE) of the grid structures is proposed and verified with EM simulations.

• Korean Chemical Engineering Research
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• 제47권1호
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• pp.1-10
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• 2009

작은 크기의 고기능성 휴대용 전자기기 수요의 급증에 따라 기존에 사용되던 수평구조의 2차원 칩의 크기를 줄이는 것은, 전기 배선의 신호지연 증가로 한계에 도달했다. 이러한 문제를 해결하기 위해 칩들을 수직으로 적층한 뒤, 수평 구조의 긴 신호배선을 짧은 수직 배선으로 만들어 신호지연을 최소화하는 3차원 칩 적층기술이 새롭게 제안되었다. 3차원 칩의 개발을 위해서는 기존에 사용되던 반도체 공정들뿐 아니라 실리콘 관통 전극 기술, 웨이퍼 박화 기술, 웨이퍼 정렬 및 본딩 기술 등의 새로운 공정들이 개발되어야 하며 위 기술들의 표준 공정을 개발하기 위한 노력이 현재 활발히 진행되고 있다. 현재까지 4~8개의 단일칩을 수직으로 적층한 DRAM/NAND 칩, 및 메모리 칩과 CPU 칩을 한꺼번에 적층한 구조의 성공적인 개발 결과가 보고되었다. 본 총설에서는 이러한 3차원 칩 적층의 기본 원리와 구조, 적층에 필요한 중요 기술들에 대한 소개, 개발 현황 및 앞으로 나아갈 방향에 대해 논의하고자 한다.

• Journal of Welding and Joining
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• 제30권3호
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• pp.26-31
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• 2012

Three-dimensional integrated circuit (3D IC) technology has become increasingly important due to the demand for high system performance and functionality. We have evaluated the effect of Buffered oxide etch (BOE) on the interfacial bonding strength of Cu-Cu pattern direct bonding. X-ray photoelectron spectroscopy (XPS) analysis of Cu surface revealed that Cu surface oxide layer was partially removed by BOE 2min. Two 8-inch Cu pattern wafers were bonded at $400^{\circ}C$ via the thermo-compression method. The interfacial adhesion energy of Cu-Cu bonding was quantitatively measured by the four-point bending method. After BOE 2min wet etching, the measured interfacial adhesion energies of pattern density for 0.06, 0.09, and 0.23 were $4.52J/m^2$, $5.06J/m^2$ and $3.42J/m^2$, respectively, which were lower than $5J/m^2$. Therefore, the effective removal of Cu surface oxide is critical to have reliable bonding quality of Cu pattern direct bonds.

• 전자공학회논문지S
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• 제35S권9호
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• pp.19-27
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• 1998

본 연구에서는 E-GSM 단말기용 RF Transceiver 칩의 송신부에 대한 회로설계 및 시뮬레이션, 공정 및 제작, 평가를 수행하였다. AMS社의 0.8${\mu}m$ BiCMOS 공정으로 제작된 RF-IC 칩은 $10 {\times} 10mm$ 크기의 80 pin TQFP로 제작되었으며, 3.3V에서 동작하고 양호한 RF 특성을 보였다. 본 논문에서는 IF/RF 상향변조 주파수 혼합기, IF/RF polyphase, 전치증폭기 등을 포함하는 송신부의 개발 결과를 서술하고자 한다. 송산단의 측정결과 E-GSM RF 송신단 주파수인 880~915MHz에서 양호하게 동작하며, 소비전류는 71mA이고 총출력은 8.2dBm으로 측정되었다.