1 |
Y.F. Tsai et al., "Three-Dimensional Cache Design Exploration Using 3DCacti," Proc. IEEE Int. Conf. Comput. Des.: VLSI Comput. Processors, San Jose, CA, USA, Oct. 2-5, 2005, pp. 519-524.
|
2 |
X. Dong and Y. Xie, "System-Level Cost Analysis and Design Exploration for Three-Dimensional Integrated Circuits (3D ICs)," Asia South Pacific Des. Autom. Conf., Yokohama, Japan, Jan. 19-22, 2009, pp. 234-241.
|
3 |
Y. Deng and W. Maly, "A Feasibility Study of 2.5D System Integration," Proc. IEEE Custom Integr. Circuits Conf., San Jose, CA, USA, Sept. 21-24, 2003, pp. 667-670.
|
4 |
X. Zhao, J. Minz, and S.K. Lim, "Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs," IEEE Trans. Compon., Packaging Manuf. Technol., vol. 1, no. 2, Feb. 2011, pp. 247-259.
DOI
|
5 |
X. Zhao and S.K. Lim, "Power and Slew-Aware Clock Network Design for Through-Silicon-Via (TSV) Based 3D ICs," Asia South Pacific Des. Autom. Conf., Taipei, Taiwan, Jan. 18-21, 2010, pp. 175-180.
|
6 |
T.Y. Kim and T.W. Kim, "Clock Tree Embedding for 3D ICs," Asia South Pacific Des. Autom. Conf., Taipei, Taiwan, Jan. 18-21, 2010, pp. 486-491.
|
7 |
International Technology Roadmap for Semiconductors (ITRS). Accessed Nov. 21, 2013. http://www.itrs.net
|
8 |
M.R. Guthaus, D. Sylvester, and R.B. Brown, "Clock Buffer and Wire Sizing Using Sequential Programming," ACM/IEEE, Des. Autom. Conf., San Francisco, CA, USA, July 24-28, 2006, pp. 1041-1046.
|
9 |
L. Xiao et al., "Local Clock Skew Minimization Using Blockage-Aware Mixed Tree-Mesh Clock Network," IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, USA, Nov. 7-11, 2010, pp. 458-462.
|
10 |
A. Rajaram, J. Hu, and R. Mahapatra, "Reducing Clock Skew Variability via Crosslinks," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 25, no. 6, June 2006, pp. 1176-1182.
DOI
|
11 |
P.J. Restle et al., "A Clock Distribution Network for Microprocessors," Symp. VLSI Circuits, Dig. Techn. Paper, Honolulu, HI, USA, June 15-17, 2000, pp. 184-187.
|
12 |
G. Venkataraman et al., "Combinatorial Algorithms for Fast Clock Mesh Optimization," IEEE Trans. Very Large Scale Integr. Syst., vol. 18, no. 1, Jan. 2010, pp. 131-141.
DOI
|
13 |
A. Rajaram and D.Z. Pan, "MeshWorks: An Efficient Framework for Planning, Synthesis and Optimization of Clock Mesh Network," Asia South Pacific Des. Autom. Conf., Seoul, Rep. of Korea, Mar. 21-24, 2008, pp. 250-257.
|
14 |
R.S. Shelar, "An Algorithm for Routing with Capacitance/Distance Constraints for Clock Distribution in Microprocessors," Int. Symp. Physical Des., San Diego, CA, USA, Mar. 29-Apr. 1, 2009. pp. 141-148.
|
15 |
A. Abdelhadi et al., "Timing-Driven Variation-Aware Nonuniform Clock Mesh Synthesis," Proc. Symp. Great Lakes Symp. VLSI, Providence, RI, USA, May 16-18, 2010, pp. 15-20.
|
16 |
M.R. Guthaus, G. Wilke, and R. Reis, "Non-uniform Clock Mesh Optimization with Linear Programming Buffer Insertion," ACM/IEEE Des. Autom. Conf., Anaheim, CA, USA, June 13-18, 2010, pp. 74-79.
|
17 |
J. Lu, X. Mao, and B. Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 31, no. 2, Feb. 2012, pp. 217-227.
DOI
|
18 |
M. Cho, D.Z. Pan, and R. Puri, "Novel Binary Linear Programming for High Performance Clock Mesh Synthesis," IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, USA, Nov. 7-11, 2010, pp. 438-443.
|
19 |
J. Lu, X. Mao, and B. Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis," Proc. Int. Symp. Physical Des., Santa Barbara, CA, USA, Mar. 27-30, 2011, pp. 131-138.
|
20 |
J. Lu, Y. Aksehir, and B. Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis," IEEE Int. Symp. Circuits Syst., Rio de Janeiro, Brazil, May 15-18, 2011, pp. 1219-1222.
|
21 |
A. Rajaram and D.Z. Pan, "MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 29, no. 12, Dec. 2010, pp. 1945-1958.
DOI
|
22 |
M.R. Guthaus et al., "High-Performance Clock Mesh Optimization," ACM Trans. Des. Autom. Electron. Syst., vol. 17, no. 3, June 2012, p. 33.
|
23 |
C. Sitik and B. Taskin, "Multi-voltage Domain Clock Mesh Design," IEEE Int. Conf. Comput. Des., Montreal, Canada, Sept. 30-Oct. 3, 2012, pp. 201-206.
|
24 |
C. Alpert and A. Devgan, "Wire Segmenting for Improved Buffer Insertion," Proc. Des. Autom. Conf., Anaheim, CA, USA, June 9-13, 1997, pp. 588-593.
|
25 |
M. You and H. Shin, "Improvement of Delay and Noise Characteristics by Buffer Insertion," IEEK, vol. 41, no. 6, June 2004, pp. 81-90.
|