• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.165-168
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• 2002

Accurate circuit simulation models for embedded RF passive components in LTCC provide a way to efficiently design high performance RF modules. Particularly, consideration of unavoidable parasitic components is required certainly. In this study, the parasitic components which is appeared from 3-D structure is considered.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.119-123
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• 2001

In this paper, a new structure and fabrication method for the wafer level package(WLP) is presented. A packaged VLSI chip is encapsulated by a parylene(which is a low k material) layer as a dielectric layer and is molded by SUB photo-epoxy with dielectric constant of 3.0 at 100 MHz. The electrical parameters (R, L, C) of package traces are extracted by using the Maxwell 3-D simulator. Based on HSPICE simulation results, the proposed wafer level package can operate for frequencies up to 20GHz.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.45-50
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• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• Journal of Welding and Joining
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• v.31 no.3
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• pp.11-16
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• 2013

Through-silicon-via (TSV) is a major technology in microelectronics for three dimensional high density packaging. The 3-dimensional TSV technology is applied to CMOS sensors, MEMS, HB-LED modules, stacked memories, power and analog, SIP and so on which can be employed to car electronics. The copper electroplating is widely used in the TSV filling process. In this paper, the various Cu filling methods using the control of the plating process were described in detail including recent studies. Via filling behavior by each method was also introduced.

• Journal of the Korean Society for Precision Engineering
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• v.26 no.12
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• pp.18-22
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• 2009

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• Journal of Sensor Science and Technology
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• v.31 no.6
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• pp.361-365
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• 2022

Advanced packaging demands are driven by the need for dense integration systems. Consequently, stacked packaging technology has been proposed instead of reducing the ultra-fine patterns to secure economic feasibility. This study proposed an effective packaging process technology for semiconductor devices using a 9-inch dicing die attach film (DDAF), wherein the die attach and dicing films were combined. The process involved three steps: tape lamination, dicing, and bonding. Following the grinding of a silicon wafer, the tape lamination process was conducted, and the DDAF was arranged. Subsequently, a silicon wafer attached to the DDAF was separated into dies employing a blade dicing process with a two-step cut. Thereafter, one separated die was bonded with the other die as a substrate at 130 ℃ for 2 s under a pressure of 2 kgf and the chip was hardened at 120 ℃ for 30 min under a pressure of 10 kPa to remove air bubbles within the DAF. Finally, a curing process was conducted at 175 ℃ for 2 h at atmospheric pressure. Upon completing the manufacturing processes, external inspections, cross-sectional analyses, and thermal stability evaluations were conducted to confirm the optimality of the proposed technology for application of the DDAF. In particular, the shear strength test was evaluated to obtain an average of 9,905 Pa from 17 samples. Consequently, a 3D integration packaging process using DDAF is expected to be utilized as an advanced packaging technology with high reliability.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.30 no.1
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• pp.63-72
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• 2024

Poly (butylene adipate-co-terephthalate) (PBAT) is one of the representative biodegradable polymers with high ductility and processability to replace petroleum-based polymers. Many investigations have been conducted to broaden the applications of PBAT in a variety of industries, including the food packaging, agricultural mulching film, and logistics and distribution fields. Foaming process is widely known technique to generate the cell structure within the polymer matrix, offering the insulation and light weight properties. However, there was no commercially feasible foam product based on biodegradable polymers, especially PBAT, and maintaining a proper melt viscosity of the polymer would be a key parameter for the foaming process. In this study, chemical foaming agent and cross-linking agent were introduced to PBAT, and a compression molding process was applied to prepare a foam sheet. The correlation between cell morphological structures and mechanical and physical properties was evaluated. It was found that PBAT with foam structures effectively reduced the density and thermal conductivity, allowing them to be suitable for applications such as insulation and lightweight packaging or cushion materials.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.229-231
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• 2007

Recently, 3D-electronic packaging by TSV is in interest. TSV(Through Silicon Via) is a interconnection hole on Si-wafer filled with conducting metal such as Copper. In this research, chips with TSV are connected by electroplated Sn bump without PR. Then chips with TSV are put together and stacked by the methode of Reflow soldering. The stacking was successfully done and had no noticeable defects. By eliminating PR process, entire process can be reduced and makes it easier to apply on commercial production.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.25 no.3
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• pp.101-109
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• 2019

The effect of packaging and storage methods in enhancing the shelf life and improving the postharvest quality of the Korean head cabbage (Brassica rapa) used for wrapping vegetables was studied at 10℃. The wrapping cabbage was packed using four types of packaging and storage materials: (A) Perforated PP film; (B) Non-perforated PP film; (C) PVC film for wrapping; and (D) non-packaged as control. The quality parameters, such as fresh appearance, weight loss, hue angle, moisture content, hardness, and SSC of wrapping cabbage were investigated. The weight loss of wrapping cabbage showed a significant difference between the one packaged with film and the non-packaged as control. The general appearance of Korean cabbage stored at 10℃ was not significantly affected by the packaging treatments. However, Korean head cabbage packaged with perforated film tend to show a better external appearance compared with those exposed to the other packaging during three weeks of storage at 10℃. The inside appearance, hue angle, moisture content, hardness, and SSC, gradually decreased during the storage period. No remarkable change in the measured items were observed in Korean cabbage packaging methods. In this experiment, the Korean cabbage packaged inside a PP film with holes, and stored at 10℃ temperature had the most desirable outcome of extending the head cabbage's shelf life and appearance quality. Results suggest that perforated packaging treatment combined with low storage temperature could be an effective method in prolonging the shelf life of Korean cabbage for wrapping vegetable.