Browse > Article

Technologies of TSV Filling and Solder Bumping for 3D Packaging  

Yoo, Se-Hoon (Micro-Joining Center, KITECH)
Ko, Young-Ki (Micro-Joining Center, KITECH)
Shin, Yue-Seon (Micro-Joining Center, KITECH)
Lee, Chang-Woo (Micro-Joining Center, KITECH)
Publication Information
Journal of the Korean Society for Precision Engineering / v.26, no.12, 2009 , pp. 18-22 More about this Journal
Keywords
Through Silicon Via; Via Filling; 3D Package; Solder Bonding;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Curran, B., Ndip, I., Guttovski, S. and Reichl, H., "Managing Losses in Through Silicon vias with Different Return Current Path Configurations," Proceedings of 10th Electronics Packaging Technology Conferences, pp. 206-211, 2008
2 Dixit, P, Chen, X., Miao, J., Divakaran, S. and Preisser, R., "Study of surface treatment processes for improvement in the wettability of silicon-based materials used in high aspect ratio through-via copper electroplating," Applied Surface Sicence, Vol. 253, No. 21, pp. 8637-8646, 2007   DOI   ScienceOn
3 Ang, X., Lin, A., Wei, J., Chen, Z. and Wong, C., "Low Temperature Copper-Copper Thermocompression Bonding," Proceedings of the Electronics Components Technology Conference, pp. 399-404, 2007
4 Chang, G. and Lee, J., "The Effect of Current Types on Through Via Hole Filling for 3D-SiP Application," Journal of the Microelectronics & Packaging Society, Vol. 13, No.4, pp. 45-50, 2006
5 Chen, K., Tan, C., Fan, A. and Reif, R., "Morphology and Bond Strength of Copper Wafer Bonding," Electrochemical Solid-State Letters, Vol. 7, No. 1, pp. G14-G16, 2004   DOI   ScienceOn
6 Tan, C., Chen, K., Fan, A. and Reif, R., "The Effect of Forming Gas Anneal on the Oxygen Content in Bonded Copper Layer," Journal of Electronic Materials, Vol. 34, No. 12, pp. 1598-1602, 2005   DOI   ScienceOn
7 Lee, S. and Lee, J., "Copper Via Filling Using Organic Additives and Wave Current Electroplating," Journal of Microelectronics & Packaging Society, Vol. 14, No.3, pp. 37-42, 2007
8 Park, S., Oh, T., Eum, Y. and Moon, J., "Interconnection Processes Using Cu Vias for MEMS Sensor Packages," Journal of the Microelectronics & Packaging Society, Vol. 14, No.4, pp. 63-69, 2007
9 Chen, N., Fan, A., Tan, C. and Reif, R., "Bonding Parameters of Blanket Copper Wafer Bonding," Journal of Electronic Materials, Vol. 35, No.2, pp. 230-234, 2006   DOI   ScienceOn
10 Sun, J., Kondo, K., Okamura, T., Oh, S., Tomisaka, M., Yonemura, H., Hoshino, M. and Takahashi, K., "High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking," Journal of the Electrochemical Society, Vol. 150, No.6, pp. 0355-0358, 2003   DOI   ScienceOn
11 Song, C., Wang, Z., Chen, Q., Cai, J. and Liu, L., "High aspect ratio copper through-silicon-vias for 3D integration," Microelectronic Engineering, Vol. 85, No. 10, pp. 1952-1956, 2008   DOI   ScienceOn
12 Jiang, T. and Luo, S., "3D Integration-Present and Future," Proceedings of 10th Electronics Packaging Technology Conferences, pp. 373-378, 2008
13 Lee, Y., Yu, J., Park, K. and Oh, T., "Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package," Journal of Electronic Materials, Vol. 38, No.5, pp. 685-690, 2009   DOI   ScienceOn
14 Chang, D., Ryu, C., Lee, K., Cho, B., Kim, J., Oh, T., Lee, W. and Yu, Y., "Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias(TSV)," Proceedings of the Electronics Components Technology conference, pp. 847-852, 2007