• Journal of the Microelectronics and Packaging Society
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• v.26 no.1
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• pp.17-21
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• 2019

In this paper, a high precision straightness measurement system has been developed at low cost using a visible laser and CMOS image sensor. CMOS image sensor detected optical image and the variation of straightness was calculated by image processing. We have observed that the error of the developed straightness measurement system was 0.9% when a distance of 3m between laser and image sensor. And it can be applied to 3D printer and any other areas.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.7-14
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• 2015

Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.711-712
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• 2009

MCP 기술을 이용한 반도체 칩에서 문제가 되는 방열문제를 해결하기 위한 방법으로 열전 냉각 소자를 이용하여 열을 방출 시키는 방법에 관하여 연구를 수행하였다. 시뮬레이션을 통하여 열전 소자가 작동할 때, 흡수하는 열량을 계산할 수 있었으며, 열전 소자의 냉각 성능도 평가 할 수 있었다. 이러한 열 해석 및 열전 해석을 통하여 적층 구조의 MCP 모듈을 위한 열 설계 및 효율적 냉각을 가능하게 할 수 있을 것이다.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.63-66
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• 2014

In this study, we investigated the effects of Cu TSV on the thermal management of 3D stacked IC. Combination of backside point-heating and IR microscopic measurement of the front-side temperature showed evolution of hot spots in thin Si wafers, implying 3D stacked IC is vulnerable to thermal interference between stacked layers. Cu TSV was found to be an effective heat path, resulting in larger high temperature area in TSV wafer than bare Si wafer, and could be used as an efficient thermal via in the thermal management of 3D stacked IC.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1587_1588
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• 2009

In this paper, PCB embedded balanced-to-unbalamced duplexer using coupled LC resonator was introduced for low cost dualband WiMax front-end-module application. In order to obtain the function of bandpass filter and balun transformer, proposed duplexer was configured by using magnetically coupled LC resonator. Out-of-band suppression was enhanced by applying two m-Derived transform circuits to obtain transmission zeros at 2GHz and 4.8GHz. In order to reduce the size of embedded duplexer, BaSrTiO3 (BST) composite high Dk RCC film was applied to improve the capacitance density. This high Dk film provided the capacitance density of 12.2 pF/mm2. The simulation results shows that fabricated duplexer had an insertion loss of 2.9dB and 5.5dB and return loss of 15dB and 16dB for 2.5GHz~2.6GHz and 3.5GHz~3.6GHz, respectively. The maximum magnitude and phase imbalance were 0.01dB and 0.17dB, and 1degree and 2degree in its passband, respectively. The out-of-band suppression was observed approximately 29dB and 40dB below 1.9GHz and over 4.5GHz, respectively. It has a volume of 6 mm $\times$ 7 mm $\times$ 0.7 mm (height).

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.69-77
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• 2016

We propose nano-scale Cu direct bonding technology using ultra-high density Cu nano-pillar (CNP) with for high stacking yield exascale 2.5D/3D integration. We clarified the joining mechanism of nano-scale Cu direct bonding using CNP. Nano-scale Cu pillar easily bond with Cu electrode by re-crystallization of CNP due to the solid phase diffusion and by morphology change of CNP to minimize interfacial energy at relatively lower temperature and pressure compared to conventional micro-scale Cu direct bonding. We confirmed for the first time that 4.3 million electrodes per die are successfully connected in series with the joining yield of 100%. The joining resistance of CNP bundle with $80{\mu}m$ height is around 30 m for each pair of $10{\mu}m$ dia. electrode. Capacitance value of CNP bundle with $3{\mu}m$ length and $80{\mu}m$ height is around 0.6fF. Eye-diagram pattern shows no degradation even at 10Gbps data rate after the lamination of anisotropic conductive film.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.75-91
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• 2006

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.71-72
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• 2012

• Journal of Welding and Joining
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• v.26 no.1
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• pp.12-16
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• 2008

본 보고에서는 3D 패키징에서 중요한 공정의 하나인 초박막 Si 웨이퍼 Thinning 공정에 대해 간략히 소개하였고, 표면처리에 대해 살펴보았다. 기계적, 특히 전기적 Damage를 줄이기 위한 최적화된 Thinning 공정과 신뢰성 분석 및 평가, 그리고 초박막 웨이퍼 핸들링 방법 등이 시스템적으로 개발되는 것이 중요하다. 칩 소형화 추세와 더불어 3D 패키징 기술이 중요시되는 산업 요구에 맞추어 향후 웨이퍼 Thinning 기술을 포함한 3D 기술의 핵심 공정기술들은 그 중요성이 증대할 것이고, 이에 대한 활발한 연구가 진행되리라 기대한다.