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http://dx.doi.org/10.6117/kmeps.2015.22.4.007

Cu Electroplating and Low Alpha Solder Bumping on TSV for 3-D Packaging  

Jung, Do hyun (Department of Materials Science and Engineering, University of Seoul)
Kumar, Santosh (Department of Materials Science and Engineering, University of Seoul)
Jung, Jae pil (Department of Materials Science and Engineering, University of Seoul)
Publication Information
Journal of the Microelectronics and Packaging Society / v.22, no.4, 2015 , pp. 7-14 More about this Journal
Abstract
Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.
Keywords
three dimensional packaging; TSV (Through Silicon Via); Cu filling; low alpha; solder bumping;
Citations & Related Records
Times Cited By KSCI : 5  (Citation Analysis)
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1 S. J. Lee, Y. J. Jang, J. H. Lee, and J. P. Jung, "Cu-Filling Behavior in TSV with Positions in Wafer Level", J. Microelectron. Packag. Soc., 21(4), 91 (2014).   DOI
2 P. Dixit, C. W. Tan, L. Xu, N. Lin, J. Miao, J. Pang, P. Backus, and R. Preisser, "Fabrication and characterization of fine pitch on-chip copper interconnects for advanced wafer level packaging by a high aspect ratio through AZ9260 resist electroplating", J. Miceomech. Microeng., 17(5), 1078 (2007).   DOI
3 S. J. Hong, J. H. Jun, J. P. Jung, and M. Mayer, "Sn Bumping Without Photoresist Mould and Si Dice Stacking for 3-D Packaging", IEEE Transactions on Advanced Packaging, 33(4), 912 (2010).   DOI
4 S. Kumar, D. H. Jung, and J. P. Jung, "Wetting behavior and elastic properties of low alpha SAC105 and pure Sn solder", J. Mater. Sci.: Mater. Electron., 24(6), 1748 (2012).   DOI
5 J. F. Ziegler and W. A. Lanford, "The effect of sea level cosmic rays on electronic devices", J. Appl. Phys., 52(6), 4305 (1981).   DOI
6 D. H. Jung, A. Sharma, K. H. Kim, Y. C. Choo, and J. P. Jung, "Effect of Current Density and Plating Time on Cu Electroplating in TSV and Low Alpha Solder Bumping", J. Mater. Eng. and Perf., 24(3), 1107 (2015).   DOI
7 J. H. Jun, I. R. Kim, M. Mayer, Y. N. Zhou, S. B. Jung, and J. P. Jung, "A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging", Materials Transactions, 51(10), 1887 (2010).   DOI
8 S. Kumar, D. H. Jung, and J. P. Jung, "High-Speed Shear Test for Low Alpha Sn-1.0%Ag-0.5%Cu (SAC-105) Solder Ball of Sub-100-${\mu}m$ Dimension for Wafer Level Packaging", IEEE Trans. Compon., Packag, Manuf. Technol., 3(3), 441 (2013).   DOI
9 S. J. Hong, Y. W. Lee, K. S. Kim, K. J. Lee, J. O. Kim, J. H. Park, and J. P. Jung, "Filling via hole in Si-wafer for 3 Dimensional Packaging", Proc. The Korean Welding and Joining Society (KWS), Samcheok, 227 (2006).
10 W. Seo, J. H. Park, J. Y. Lee, M. K. Cho, and G. S. Kim, "Via Cleaning Process for Laser TSV Process", J. Microelectron. Packag. Soc., 16(1), 45 (2009).
11 H. Lee, M. Choi, S. H. Kwon, J. H. Lee, and Y. Kim, "Characteristic of Through Silicon Via's Seed Layer Deposition and Via Filling". Kor. J. Mater. Res, 23(10), 550 (2013).   DOI
12 S. P. Shen, W. H. Chen, W. P. Dow, T. Kamitamari, E. Cheng, J. Y. Lin, and W. C. Chang, "Copper seed layer repair using an electroplating process for through silicon via metallization", Microelectronic Engineering, 105, 25 (2013).   DOI
13 T. Kenji, T. Hiroshi, T. Yoshihiro, Y. Yasuhiro, H. Masataka, S. Tomotoshi, M. Tadahiro, and B. Manabu, "Current status of research and development for three-dimensional chip stack technology", J. Appl. Phys., 40, 3032 (2001).   DOI
14 R. Lee, R. Hon, and C. K. Wong, "3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling", Proc. 55th Elec. Pack. Tech. Conf. (EPTC), Lake Buena Vista, 795 (2005).
15 B. H. Kim, H. C. Kim, K. J. Chun, J. H. Ki, and Y. S. Tak, "Cantilevert-type microelectromechanical systems probe card with through-wafer interconnects for fine pitch and highspeed testing", J. Applied Physics, 43(6B), 3877 (2004).   DOI
16 F. Inoue, H. Philipsen, A. Radisic, S. Armini, Y. Civale, P. Leunissen, M. Kondo, E. Webb, and S. Shingubara, "Electroless Cu deposition on atomic layer deposited Ru as novel seed formation process in through-Si vias", Electrochimica Acta, 100(30), 203 (2013).   DOI
17 M. Knaut, M. Junige, V. Neumann, H. Wojcik, T. Henke, C. Hossbach, A. Hiess, M. Albert, and J. W. Bartha, "Atomic layer deposition for high aspect ratio through silicon vias", Microelec. Eng., 107, 80 (2013).   DOI
18 S. Yamamoto, K. Itoi, T. Suemasu, and T. Takizawa, "Si through-hole interconnections filled with Au-Sn solder by molten metal suction method", Proc. 16th IEEE International Conference, Kyoto, 642 (2003).
19 T. Hayashi, K. Kondo, T. Saito, M. Takeuchi, and N. Okamoto, "High-Speed Through Silicon Via(TSV) Filling Using Diallylamine Additive", J. Electrochem. Soc., 158(12), 715 (2011).
20 C. Lee, S. Tsuru, Y. Kanda, S. Ikeda, and M. Matsumura, "Formation of 100-${\mu}m$-deep Vertical Pores in Si Wafers by Wet Etching and Cu Electrodeposition", J. Electrochem. Soc., 156(12), D543 (2009).   DOI
21 H. Y. Li, E. Liao, X. F. Pang, H. Yu, X. X. Yu, and J. Y. Sun, "Fast Electroplating TSV Process Development for the Via-Last Approach", Proc. 60th Electronic Components and Technology Conference (ECTC), Las Vegas, 777, IEEE Components (2010).
22 H. Banha, A. Funabashi, and F. Kondo, "High speed TSV filling", Proc. 24th Micro Electron. Sympo. (MES), Osaka, 53 (2015).
23 A. Pohjoranta and R. Tenno, "A Method for Microvia-Fill Process Modeling in a Cu Plating System with Additives", J. Electrochem. Soc., 154(10), D502 (2007).   DOI
24 I. R. Kim, S. C. Hong, and J. P. Jung, "High Speed Cu Filling into Tapered TSV for 3-dimensional Si Chip Stacking", J. Met. Mater., 49(5), 388 (2010).
25 I. R. Kim, J. K. Park, Y. C. Chu, and J. P. Jung, "High speed Cu Filling Into TSV by Pulse Current for 3 Dimensional Chip Stacking", J. Met. Mater., 48(7), 667 (2010).
26 S. C. Hong, W. G. Lee, W. J. Kim, J. H. Kim, and J. P. Jung, "Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking", Microelectronics Reliability, 51, 2228 (2011).   DOI
27 S. C. Hong, D. H. Jung, J. P. Jung, and W. J. Kim, "Effective Cu Filling Method to TSV for 3-dimensional Si Chip Stacking", Korean J. Met. Mater., 50(2), 152 (2012).   DOI