• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.93-100
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• 2009

This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.6
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• pp.419-427
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• 2019

Several multilevel converter topologies have been proposed and compared. The three-level (3L) neutral-point-clamped (NPC) topology is promising and widely accepted. However, this topology suffers from uneven loss distribution among switches due to its fixed switching strategy. The 3L active NPC (ANPC) topology, which exhibits improved loss distribution profile, was proposed to address this disadvantage. The 3L T-NPC topology, a hybrid configuration of 2L and 3L NPC topologies, was introduced to address not only the loss distribution problem but also the reduction in the number of switches. In the present research, the application of these three topologies in PMSG-based medium-voltage wind turbines was investigated. The power devices considered were 10 kV IGCTs. Performance was evaluated in terms of a power loss of 10 kV IGCT for each NPC topology, which is a crucial indicator of thermal behavior, reliability, cost, and lifetime of any converter. The comparison was performed using ABB make 10 kV IGCT 5SHY17L9000 and the simulation tool PLECS.

• Journal of IKEEE
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• v.18 no.4
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• pp.586-592
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• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.149-150
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• 2011

본 논문에서는 3-Level Vienna Converter를 간단히 제어 하기 위한 단일 반송파 비교 방식의 전압제어 방법을 제안 한다. 제안된 전압 제어 방식은 Two-Level 전압 변조 방식의 상전압 지령과 단자 전압 지령은 그대로 사용하고, 삼각파 비교부만 비엔나 정류기에 적합하게 단일 반송파를 이용한 방식으로 바꿔 SVPWM을 간단하게 구현할 수 있으며, 기존의 Two-Level 컨버터에서 적용하던 다양한 선형 변조 및 과변조 방식 등 전압제어 알고리듬과 전류제어 알고리듬 등을 Three - Level 컨버터에 쉽게 적용 할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.1-9
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• 2008

This paper suggests the triple-mode CMOS DC-DC converter that has temperature/voltage variation compensation techniques. The proposed triple-mode CMOS DC-DC converter is used to generate constant or variable voltages of 0.6-2.2V within battery source range of 3.3-5.5V. Also, it supports triple modes, which include Pulse Width Modulator (PWM) mode, Pulse Frequency Modulator (PFM) mode and Low Drop-Out (LDO) mode. Moreover, it uses 1MHz low-power CMOS ring oscillator that will compensate malfunction of chip in temperature/voltage variation condition. The proposed triple-mode CMOS DC-DC converter, which generates output voltages of 0.6-2.2V with an input voltage sources of 3.3-5.5V, exhibits the maximum output ripple voltage of below 10mV at PWM mode, 15mV at PFM mode and 4mV at LDO mode. And the proposed converter has maximum efficiency of 93% at PWM mode. Even at $-25{\sim}80^{\circ}C$ temperature variations, it has kept the output voltage level within 0.8% at PWM/PFM/LDO modes. For the verification of proposed triple-mode CMOS DC-DC converter, the simulations are carried out with $0.35{\mu}m$ CMOS technology and chip test is carried out.

• Journal of Power Electronics
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• v.11 no.4
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• pp.591-598
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• 2011

This paper investigates a power supply of medium voltage with enhanced ignition characteristics for plasma torches. A series resonant half-bridge topology is presented as a suitable ignition circuitry. The ignition circuitry is integrated into the main power conversion system of a multi-phase staggered three-level dc-dc converter with a diode front-end rectifier. A plasma torch rated at 3MW, 2kA and having a physical size of 1m is selected to be the high enthalpy source for a waste disposal system. The steady-state and transient operations of a plasma torch are simulated. The parameters of a Cassie-Mary arc model are calculated based on 3D magneto-hydrodynamic simulations. The circuit simulation waveform shows that the ripple of the arc current can be maintained within ${\pm}10%$ of its rated value under the presence of a load disturbance. This power conversion configuration provides a high enough ignition voltage, around 5KA, during the ignition phase and high arc stability under the existence of arc disturbance noise resulting in a high-performance plasma torch system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.161-162
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• 2015

본 논문은 수중음향센서용 전력증폭기를 위한 멀티레벨 가변 출력전압 AC/DC 컨버터를 제안한다. 제안하는 AC/DC 컨버터는 멀티레벨 가변출력전압을 얻기 위해 2개의 flying-capacitor 3-level converters와 하나의 다이오드 브리지 회로로 구성되어 있다. 또한 본 논문에서는 제안하는 AC/DC 컨버터의 상세 회로도와 설계 가이드라인을 제시하였다.

• Journal of IKEEE
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• v.22 no.4
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• pp.1006-1011
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• 2018

This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.3
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• pp.13-18
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• 2010

This work proposes and characterizes switched-capacitor type cyclic digital-to-analog converter for display data driving. The proposed digital-to-analog converter composes simple structure, and can be implemented for low-power, small area display driver ICs. By circuit level simulations, it is verified that the op-amp input referred offset is attenuated at the DAC output and the circuit performance is robust at 0.5% of capacitor mismatch.