• Title/Summary/Keyword: 2-level inverter

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The DC-link Voltage Balancing of the Three-Level T-type Inverter Using the Predictive Control (예측제어를 이용한 T-형 3-레벨 인버터의 중성점 전압제어)

  • Kim, Tae-Hun;Lee, Woo-Cheol
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.2
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    • pp.311-318
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    • 2016
  • This paper is a study on the neutral point voltage balancing of the three-phase 3-level T-type inverter using the predictive control techniques. Recently, multi-level inverter has been attracting attention as the advantages such as efficiency improving and harmonic reduction. Especially, the T-type inverter topology is advantageous in low DC-link voltage. However, in case of the prediction control, it takes a lot of time, because there exist 27 voltage vectors and it has to be calculated according to the respective voltage vectors. Therefore, in this paper, we propose a method to implement predictive control techniques while reducing the operation time. In order to reduce the operation time, the predictive control is implemented by using the minimum voltage vector except for the unnecessary voltage vector. The result of the implemented predictive control is added to the SPWM by using the offset voltage. It was verified through simulation and experimental results.

Overmodulation Operation of SVM for NPC Type 3-Level Inverter (NPC형 3레벨 인버터의 공간벡터 과변조운전)

  • Lee, Jae-Moon;Choi, Jae-Ho
    • The Transactions of the Korean Institute of Power Electronics
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    • v.13 no.1
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    • pp.22-32
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    • 2008
  • This paper proposes a linearization technique for the 3-level NPC type inverter, which increases the linear control range of Inverter up to the one-pulse inverter. The overmodulation range is divided into two modes depending on the Modulation Index, MI. In overmodulation region I, the reference angles are derived from the fourier series expansion of the reference voltage corresponding to the MI. In overmodulation region II, the holding angles are also derived in the same way. Therefore, it is possible to obtain the linear control and the maximized utilization of PWM inverter output voltage.

Auxiliary Resonant Commutated Leg Snubber Linked 3-Level 3-Phase Voltage Source Soft-Switching Inverter

  • Yamamoto, Masayoshi;Sato, Shinji;Hiraki, Eiji;Nakaoka, Mutsuo
    • Journal of Power Electronics
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    • v.3 no.2
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    • pp.90-98
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    • 2003
  • This paper presents a performance analysis in steady-state of a novel type Auxiliary Resonant Commutation Snubber-linked 3-level 3-phase voltage source soft switching inverter suitable and acceptable for high-power applications in comparison with other three types of 3-level 3-phase voltage source soft switching inverters. This soft switching inverter operation which can operate under a condition of Zero Voltage Switching (ZVS). The practical steady -state performances of this inverter are illustrated and evaluated on the basis of the experimental results.

3-Level T-type Inverter Operation Method Using Level Change

  • Kim, Tae-Hun;Lee, Woo-Cheol
    • Journal of Electrical Engineering and Technology
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    • v.13 no.1
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    • pp.263-269
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    • 2018
  • In this study, a selective inverter operation between a 2-level voltage source converter (VSC) and a 3-level T-type VSC (3LT VSC) is proposed to improve the efficiency of a 3LT VSC. The 3LT VSC topology, except for its neutral-point switches, has similar operations as that of the 2-level VSC. If an operation mode is changed according to efficiency, the efficiency can be improved because efficiencies of each methods are depending on current and MI (Modulation Index). The proposed method calculates the power losses of the two topologies and operates as the having lower losses. To calculate the losses, the switching and conduction losses based on the operation mode of each topology were analyzed. The controller determined the operation mode of the 2- or 3-level VSC based on the power loss calculated during every cycle. The validity of the proposed control scheme was investigated through simulation and experiments. The waveform and average efficiency of each method were compared.

Torque ripple reduction in DTC of induction motor driven by 3-level inverter (3레벨 인버터로 구동되는 유도전동기 직접토크제어의 토크리플 저감법)

  • Lee, Kyo-Beum;Song, Joong-Ho;Choy, Ick;Yoo, Ji-Yoon
    • The Transactions of the Korean Institute of Power Electronics
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    • v.5 no.6
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    • pp.620-631
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    • 2000
  • A torque ripple reduction technique of direct torque control(DTC) for high power induction motors driven by 3-level inverters with the inverter switching frequency limited around 0.5-1.0kHz level is presented. It is noted that conventional DTC algorithms to reduce torque ripple are devised for applications with relatively high switching frequency above 2-3kHz. Such conventional algorithms can not accomplish satisfactory torque ripple reduction for 3-level inverter systems with lower switching frequency. A new DTC algorithm, especially for low switching frequency inverter system, illustrates relatively reduced torque ripple characteristics all over the operating speed region. Simulation and experimental results show the effectiveness of the proposed control algorithm.

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A Method to Compensate the Distorted Space Vectors in the Unbalanced Neutral Point Voltage of 3-level NPC PWM Inverters

  • Hyun, Seung-Wook;Hong, Seok-Jin;Lee, Jung-Hyo;Lee, Chun-Bok;Won, Chung-Yuen
    • Journal of Power Electronics
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    • v.16 no.2
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    • pp.455-463
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    • 2016
  • This paper proposes a compensation method to improve the distorted space vectors when a 3-level Neutral Point Clamped (NPC) inverter has an unbalanced neutral point voltage. Since both the neutral point voltage of the DC link and the space vector of a 3-level NPC inverter are closely related depending on the output load connecting state, a distorted space vector can occur when the neutral point voltage of a 3-level NPC inverter is unbalanced. The proposed method can improve the distorted space vectors by adjusting the injection time of the small and medium vectors and by modulating the amplitude of the carrier waveforms. In this paper, the proposed method is verified by both simulation and experimental results based on a 3-level NPC inverter.

Harmonic Optimization Techniques in Multi-Level Voltage-Source Inverter with Unequal DC Sources

  • Aghdam, M. Ghasem Hosseini;Fathi, S. Hamid;Gharehpetian, Gevorg B.
    • Journal of Power Electronics
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    • v.8 no.2
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    • pp.171-180
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    • 2008
  • One of the major problems in electric power quality is the harmonic contents. There are several methods of indicating the quantity of harmonic contents. The most widely used measure is the total harmonic distortion (THD). Various switching techniques have been used in static converters to reduce the output harmonic content. This paper presents and compares the two harmonic optimization techniques, known as optimal minimization of the total harmonic distortion (OMTHD) technique and optimized harmonic stepped-waveform (OHSW) technique used in multi-level inverters with unequal dc sources. Both techniques are very effective and efficient for improving the quality of the inverter output voltage. First, we describe briefly the cascaded H-bridge multi-level inverter structure. Then, we present the switching algorithm for the inverter based on OHSW and OMTHD techniques. Finally, the results obtained for the two techniques are analyzed and compared. The results verify the effectiveness of the both techniques in multi-level voltage-source inverter with non-equal dc sources, clarifying the advantages of each technique.

Development of a Switched Diode Asymmetric Multilevel Inverter Topology

  • Karthikeyan, D.;Krishnasamy, Vijayakumar;Sathik, Mohd. Ali Jagabar
    • Journal of Power Electronics
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    • v.18 no.2
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    • pp.418-431
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    • 2018
  • This paper presents a new asymmetrical multilevel inverter with a reduced number of power electronic components. The proposed multilevel inverter is analyzed using two different configurations: i) First Configuration (with a switched diode) and ii) Second Configuration (without a switched diode). The presented topologies are compared with recent multilevel inverter topologies in terms of number of switches, gate driver circuits and blocking voltages. The proposed topologies can be cascaded to generate the maximum number of output voltage levels and they are suitable for high voltage applications. Various power quality issues are addressed for both of the configurations. The proposed 11-level inverter configuration is simulated using MATLAB and it is validated with a laboratory based experimental setup.

The Development of Double Conversion Uninterruptible Power Supply Using 3-Level Converter/TNPC Inverter (3-레벨 부스트 컨버터/TNPC 인버터를 적용한 이중변환 무정전전원장치 개발)

  • Byeon, Yong Seop;Lim, Seung Beom;Choi, Kyu Hyuk;Hong, Soon Chan;Lee, Jun Young
    • Proceedings of the KIPE Conference
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    • 2014.07a
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    • pp.83-84
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    • 2014
  • This paper proposes the development of double conversion Uninterruptible Power Supply using 3-Level Converter/TNPC Inverter. The Rectifier of proposed system is operating not only 3-Level boost PFC but also battery discharger. The Inverter is converting DC voltage to AC voltage. And in terms of the efficiency, 3-Level TNPC inverter is improved compared to the origin 2-Level type. To verify the validity of proposed system, experiments were carried out.

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Basic Characteristic of 5-level Inverter with Different Divided DC Link Voltage

  • Matsuse, Kouki;Matsumoto, Takafumi;Kodera, Yuji
    • Journal of international Conference on Electrical Machines and Systems
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    • v.2 no.2
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    • pp.179-183
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    • 2013
  • This paper report on experimental results of 5-level inverter by DC divided link voltage. We have alreday reported that DC divided link valtage comes to be able to reduse harmonic of out line voltage. So we tested whether DC divided link voltage can reduce harmonics in experimental setup. This paper shows simulation results and experimental results. And we confirmed that DC divided link voltage can also apply in experimental setup.