• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.62-68
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• 2007

This paper proposes an efficient integer division algorithm for high speed FPGAs' which support built-in RAMs' and multipliers. The integer division algorithm is iterative with RAM-based LUT and multipliers, which minimizes the usage of logic fabric and connection resources. Compared with some popular division algorithms such as division by subtraction or division by multiply-subtraction, the number of iteration is much smaller, so that very low latency can be achieved with pipelined implementations. We have implemented our algorithm in the Xilinx virtex-4 FPGA with VHDL coding and have achieved 300MSPS data rate in 17bit integer division. The algorithm used less than 1/6 of logic slices, 1/4 of the built-in multiply-accumulation units, and 1/3 of the latencies compared with other popular algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.1-6
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• 2002

In this paper, an Analog Flat Panel interface(AFPI) which supports for UXGa(Ultar extended Graphics Array)-Compatible TFT LCD Driver is designed. The Proposed AFPI is composed of 8-b ADC, Automatic Gain Control(AGC), Low-Jitter PLL. In order to obtain a high speed and low power consumption, an efficient architecture of 8-bit ADC is proposed, whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 2, and IR (Interpolating Rate) is 16. We can get high SNDR by adopting distributed track and hold circuits. Also a programmable AGC which is possible to control gain and clamp, and a low-jitter PLL are proposed. The chip has been fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly S-metal n-well CMOS technology. The effective chip area is 3.6mm $\times$ 3.2mm and it dissipates about 602㎽ at 2.5V power supply. The INL and DNL are within $\pm$ 1LSB. The measured SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1820-1826
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• 2001

In this paper, we present a modeling scheme for the already-installed two-wire home phone lines with arbitrary topologies and show that the inter-symbol interference due to the topology can be removed using an adaptive equalizer. The transmission characteristics of the arbitrary-configured two-wire home phone lines can be analyzed through the ABCD matrices. The simulation result shows that the impedance mismatch due to the branch lines renders nulls in the frequency response or delayed pulses in the impulse response. These nulls or delayed pulses cause inter-symbol interference that inhibits correct signal detection. An adaptive equalizer is shown to be effective in eliminating the interference. Also, the simulation result shows that the equalizer converges in 1.5 ms at a data rate of 1 Msps at signal-to-noise ratios greater than 15 dB. In addition, from the result of relation between E$\_$b//N$\_$and BER(Bit Error Rate), we can see that E$\_$b//N$\_$o/ more than 19 dB is required for the data communication with a BER less than 10$\^$-5/.

• Parasites, Hosts and Diseases
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• v.53 no.2
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• pp.177-187
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• 2015

Merozoite surface proteins (MSPs) of malaria parasites play critical roles during the erythrocyte invasion and so are potential candidates for malaria vaccine development. However, because MSPs are often under strong immune selection, they can exhibit extensive genetic diversity. The gene encoding the merozoite surface protein-3 (MSP-3) of Plasmodium falciparum displays 2 allelic types, K1 and 3D7. In Thailand, the allelic frequency of the P. falciparum msp-3 gene was evaluated in a single P. falciparum population in Tak at the Thailand and Myanmar border. However, no study has yet looked at the extent of genetic diversity of the msp-3 gene in P. falciparum populations in other localities. Here, we genotyped the msp-3 alleles of 63 P. falciparum samples collected from 5 geographical populations along the borders of Thailand with 3 neighboring countries (Myanmar, Laos, and Cambodia). Our study indicated that the K1 and 3D7 alleles co-existed, but at different proportions in different Thai P. falciparum populations. K1 was more prevalent in populations at the Thailand-Myanmar and Thailand-Cambodia borders, whilst 3D7 was more prevalent at the Thailand-Laos border. Global analysis of the msp-3 allele frequencies revealed that proportions of K1 and 3D7 alleles of msp-3 also varied in different continents, suggesting the divergence of malaria parasite populations. In conclusion, the variation in the msp-3 allelic patterns of P. falciparum in Thailand provides fundamental knowledge for inferring the P. falciparum population structure and for the best design of msp-3 based malaria vaccines.

• Journal of Navigation and Port Research
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• v.42 no.5
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• pp.311-316
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• 2018

IMO introduced the concept of e-Navigation and proposed MSPs(Maritime Service Portfolios) concept to reduce marine accidents, to improve efficiency of ship operation, port operation, and ship operation technology. Korean e-Navigation defines S1 ~ S5 services, as the service concept focused on domestic e-Navigation service corresponding to IMO MSPs, and is constructing a system as an ongoing project. S2 service (onboard system remote monitoring service) among the concepts of Korean e-Navigation services, is a service concept that judges the emergency level according to risk if an abnormal condition occurs during navigation, and provides corresponding guidance to accident ships based on emergency level. The purpose of this paper is to provide a basic architecture proposal of Korean e-Navigation S2 service navigation safety module, based on the S2 service operation concept. To do this, we conducted a questionnaire survey to ask experts with experience with sailors, to respond to the subjective risk experienced by sailors considering effects of anomalies, including equipment failure relative to sailing and navigational safety. Risk level for each abnormal condition was classified. The basic algorithm design of the navigation safety module is composed of safety index (SI) calculation module based on results of questionnaire and expert opinions, safety level (SL) determination module according to safety index, and corresponding guidance generation module according to safety level. To conduct basic validation of basic architecture of the navigation safety module, simulation of the ship anomaly monitoring was performed, and results have been revealed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2100-2106
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• 2007

Multi-stage folding A/D converter circuit with $0.25{\mu}m$ N-well CMOS technology is designed. This A/D converter consists of a transconductance circuit, linear folder circuit and 1bit A/D converter circuit. In H-spice simulation results, linear folder circuits having high linearity can be obtained when the current mode is used instead of voltage mode. And in case of 6bit, the delay time is limited about 40ns. From this results, 6bit 25MSPS A/D converter circuit can be realized.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.47-55
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• 2010

In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

• Journal of the Korea Convergence Society
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• v.8 no.7
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• pp.1-6
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• 2017

This paper presents the design of a frequency measurement device using ADC, EP2AGX FPGA and STM32 processor to accurately measure the frequency of a broadband high frequency signal. The ADC device used in this paper has a sampling frequency of 250 MSPS and a processing frequency bandwidth of 100 MHz. Due to its high sampling frequency, it is difficult to process in ordinary computers or processors, so we implemented the frequency measurement algorithm using the Altra EP2AGX FPGA. The measured frequency is sent to the direction detection controller in real time and fused with the phase signal to calculate the incident azimuth angle of the high frequency signal. The designed frequency measurement device is about 0.2 Mhz in frequency measurement error and 30% less than Anaren DFD-x, which is considered to contribute greatly to the design of radio monitoring and direction detection device.