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Design of an 8-bit 230MSPS Analog Flat Panel Interface for TFT-LCD Driver  

Yun, Seong-Uk (삼성탈레스 기술개발팀)
Im, Hyeon-Sik (동국대학교 반도체과학과)
Song, Min-Gyu (동국대학교 반도체과학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.2, 2002 , pp. 1-6 More about this Journal
Abstract
In this paper, an Analog Flat Panel interface(AFPI) which supports for UXGa(Ultar extended Graphics Array)-Compatible TFT LCD Driver is designed. The Proposed AFPI is composed of 8-b ADC, Automatic Gain Control(AGC), Low-Jitter PLL. In order to obtain a high speed and low power consumption, an efficient architecture of 8-bit ADC is proposed, whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 2, and IR (Interpolating Rate) is 16. We can get high SNDR by adopting distributed track and hold circuits. Also a programmable AGC which is possible to control gain and clamp, and a low-jitter PLL are proposed. The chip has been fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly S-metal n-well CMOS technology. The effective chip area is 3.6mm $\times$ 3.2mm and it dissipates about 602㎽ at 2.5V power supply. The INL and DNL are within $\pm$ 1LSB. The measured SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.
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