• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.423-424
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• 2011

This paper has proposed a 920 MHz RF front-end for IEEE 802.15.4g SUN (Smart Utility Network) systems. The proposed 920 MHz RF front-end consists of a driver amplifier, a low noise amplifier, and a RF switch. In the TX mode, the driver amplifier has been designed as a single-ended topology to remove a transformer which causes a loss of the output power from the driver amplifier. In addition, a RF switch is located in the RX path not the TX path. In the RX mode, the proposed low noise amplifier can provide a differential output signal when a single-ended input signal has been applied to. A LC resonant circuit is used as both a load of the drive amplifier and a input matching circuit of the low noise amplifier, reducing the chip area. The proposed 920 MHz RF Front-end has been implemented in a 0.18-um CMOS technology. It consumes 3.6 mA in driver amplifier and 3.1 mA in low noise amplifier from a 1.8 V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.174-179
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• 2013

This paper presents a capacitor loaded tunable bandpass chip filter using multiple split ring resonators (MSRRs) with two transmission zeros. To obtain high selectivity and minimize the chip size, asymmetric feed lines are adopted to make a pair of transmission zeros located on each side of passband. Compared with conventional filters using cross-coupling or source-load coupling techniques, the proposed filter uses only two resonators to achieve high selectivity through a pair of transmission zeros. In order to optimize selectivity and sensitivity (insertion loss) of the filter, the effect of the position of asymmetric feed line on transmission zeros and insertion loss is analyzed. The SOI-CMOS switched capacitor composed of metal-insulator-metal (MIM) capacitor and stacked-FETs is loaded at outer rings of MSRRs to tune passband frequency and handle high power signal up to +30 dBm. By turning on or off the gate of the transistors, the passband frequency can be shifted from 4GH to 5GHz. The proposed on-chip filter is implemented in 0.18-${\mu}m$ SOI CMOS technology that makes it possible to integrate high-Q passive devices and stacked-FETs. The designed filter shows miniaturized size of only $4mm{\times}2mm$ (i.e., $0.177{\lambda}g{\times}0.088{\lambda}g$), where ${\lambda}g$ denotes the guided wave length of the $50{\Omega}$ microstrip line at center frequency. The measured insertion loss (S21)is about 5.1dB and 6.9dB at 5.4GHz and 4.5GHz, respectively. The designed filter shows out-of-band rejection greater than 20dB at 500MHz offset from center frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.1-8
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• 2000

In this paper, the dependence of interconnect line-induced delay time on the size of CMOSFET gate width is characterized. In case of capacitance dominant interconnect line, the total delay time decreases as transistor size increases. However, there exists a transistor size for minimum total delay time when both of resistance and capacitance of interconnect line become larger than those of transistor. The optimum transistor size for minimum total delay time is obtained using an analytic equation and the experimental results showed good agreement with the calculation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.202-207
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• 2015

A CMOS relaxation oscillator, with high robustness over process, voltage and temperature (PVT) variations, is designed in $0.18{\mu}m$ CMOS. The proposed oscillator, consisting of full-differential charge-discharge timing circuit and switched-capacitor based voltage-to-current conversion, could be expanded to a simple open-loop frequency synthesizer (FS) with output frequency digitally tuned. Experimental results show that the proposed oscillator conducts subcarrier generation for frequency-modulated ultra-wideband (FM-UWB) transmitters with triangular amplitude distortion less than 1%, and achieves frequency deviation less than 8% under PVT and phase noise of -112 dBc/Hz at 1 MHz offset frequency. Under oscillation frequency of 10.5 MHz, the presented design has the relative FS error less than 2% for subcarrier generation and the power dissipation of 0.6 mW from a 1.8 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.2
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• pp.104-110
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• 2019

In this paper, a complementary metal oxide semiconductor(CMOS) power amplifier(PA) integrated circuit operating in the 900 MHz band for long-term evolution(LTE) communication systems is presented. The output matching network based on a transformer was implemented on a printed circuit board for low loss. Simultaneously, to achieve high efficiency of the PA, the second harmonic impedances are controlled. The CMOS PA was fabricated using a $0.18{\mu}m$ CMOS process and measured using an LTE uplink signal with a bandwidth of 10 MHz and peak to average power ratio of 7.2 dB for verification. The implemented CMOS PA module exhibits a power gain of 24.4 dB, power-added efficiency of 34.2%, and an adjacent channel leakage ratio of -30.1 dBc at an average output power level of 24.3 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.825-833
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• 2016

This paper introduces a direct-conversion CMOS RF transmitter for the IEEE 802.15.4 standard with a low-power high-gain up-conversion mixer designed in $0.18{\mu}m$ process. The designed RF DCT(Direct Conversion Transmitter) is composed of differential DAC(Digital to Analog Converter), passive low-pass filter, quadrature active mixer and drive amplifier. The most important characteristic in designing RF DCT is to satisfy the 2.4 GHz Zigbee standard in low power. The quadrature active mixer inside the proposed RF DCT provides enough high gain as well as sufficient linearity using a gain boosting technique. The measurement results for the proposed transmitter show very low power consumption of 7.8 mA, output power more than 0 dBm and ACPR (Adjacent Channel Power Ratio) of -30 dBc.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.212-215
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• 2016

In this paper, a 5.08 GHz Ring Voltage Controlled Oscillator(Ring VCO) was implemented using $0.18{\mu}m$ standard CMOS technology. The proposal Ring VCO is 3-stage structure. This research confirmed that the each stage's different transistor size ratio influence the current change and alter power consumption consequentially. This circuit is formed to control the current thereby adding the Current Mirror and to tune the frequency by supplying control voltage. It has an 65.5 %(1.88~5.45 GHz) tuning range. The measured output power is -0.30 dBm. The phase noise is -87.50 dBc/Hz @1 MHz offset with operating frequency of 5.08 GHz fundamental frequency. The total power consumption of Ring VCO is 31.2 mW with 2.4 V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.267-273
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• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.32-38
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• 2011

This paper describes implementation of the 5.0GHz RF frequency synthesizer with 0.18${\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get excellent performance of high speed and wide tuning range, N-P MOS core structure and 12 step cap banks have been used in design of the VCO. The chip area including pads for testing is $1.1{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.0{\times}0.4mm^2$. Through analysing of the fabricated frequency synthesizer, we can see that it has wide operation range and excellent frequency characteristics.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.