• Title/Summary/Keyword: 플립칩 범프 본딩

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Flip Chip Process on CNT-Ag Composite Pads for Stretchable Electronic Packaging (신축성 전자패키징을 위한 CNT-Ag 복합패드에서의 플립칩 공정)

  • Choi, Jung Yeol;Oh, Tae Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.4
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    • pp.17-23
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    • 2013
  • As a basic research to develop stretchable electronic packaging technology, CNT-Ag composite pads were formed on top of Cu/Sn chip bumps and flip-chip bonded using anisotropic conductive adhesive. Average contact resistances of the flip-chip joints were measured with respect to bonding pressure and presence of the CNT-Ag composite pads. When Cu/Sn chip bumps with CNT-Ag composite pads were flip-chip bonded to substrate Cu pads at 25MPa or 50 MPa, contact resistance was too high to measure. The specimen processed by flip-chip bonding the Cu/Sn chip bumps with CNT-Ag composite pads to the substrate Cu pads exhibited an average contact resistance of $213m{\Omega}$. On the other hand, the flip-chip specimens processed by bonding Cu/Sn chip bumps without CNT-Ag composite pads to substrate Cu pads at 25MPa, 50MPa, and 100MPa exhibited average contact resistances of $370m{\Omega}$, $372m{\Omega}$, and $112m{\Omega}$, respectively.

Numerical Analysis of Warpage Induced by Thermo-Compression Bonding Process of Cu Pillar Bump Flip Chip Package (수치해석을 이용한 구리기둥 범프 플립칩 패키지의 열압착 접합 공정 시 발생하는 휨 연구)

  • Kwon, Oh Young;Jung, Hoon Sun;Lee, Jung Hoon;Choa, Sung-Hoon
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.41 no.6
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    • pp.443-453
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    • 2017
  • In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.

COG 플립칩 본딩 공정조건에 따른 Au-ITO 접합부 특성

  • Choe, Won-Jeong;Min, Gyeong-Eun;Han, Min-Gyu;Kim, Mok-Sun;Kim, Jun-Gi
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2011.05a
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    • pp.64.1-64.1
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    • 2011
  • LCD 디스플레이 등에 사용되는 글래스 패널 위에 bare si die를 직접 실장하는 COG 플립칩 패키지의 경우 Au 범프와 ITO 패드 간의 전기적 접속 및 접합부 신뢰성 확보를 위해 접속소재로서 ACF (anisotropic conductive film)가 사용되고 있다. 그러나 ACF는 고가이고 접속피치 미세화에 따라 브릿지 형상에 의한 쇼트 등의 문제가 발행할 수 있어 NCP (non-conductive paste)의 상용화가 요구되고 있다. 본 연구에서는 NCP를 적용한 COG 패키지에 있어서 온도, 압력 등의 열압착 본딩 조건과 NCP 물성이 Au-ITO 접합부의 전기적 및 기계적 특성에 미치는 영향을 조사하였다. NCP는 에폭시 레진과 경화제, 촉매제를 사용하여 다양하게 포뮬레이션을 하였고 DSC (Differential Scanning Calorimeter), TGA (Thermogravimetric Analysis), DEA (Dielectric Analysis) 등의 열분석장비를 이용하여 NCP의 물성과 경화 거동을 확인하였다. 테스트 베드는 면적 $5.2{\times}7.2\;mm^2$, 두께 650 ${\mu}m$, 접속피치 200 ${\mu}m$의 Au범프가 형성된 플립칩 실리콘 다이와 접속패드가 ITO로 finish된 글래스 기판을 사용하였다. 글래스 기판과 실리콘 칩은 본딩 전 PVA Tepla사의 Microwave 플라즈마 장비로 Ar, $O_2$ 플라즈마 처리를 하였으며, Panasonic FCB-3 플립칩 본더를 사용하여 본딩하였다. 본딩 후 접합면의 보이드를 평가하고 die 전단강도로 접합강도를 측정하였다.

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Study of micro flip-chip process using ABL bumps (ABL 범프를 이용한 마이크로 플립 칩 공정 연구)

  • Ma, Junsung;Kim, Sungdong;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.21 no.2
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    • pp.37-41
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    • 2014
  • One of the important developments in next generation electronic devices is the technology for power delivery and heat dissipation. In this study, the Cu-to-Cu flip chip bonding process was evaluated using the square ABL power bumps and circular I/O bumps. The difference in bump height after Cu electroplating followed by CMP process was about $0.3{\sim}0.5{\mu}m$ and the bump height after Cu electroplating only was about $1.1{\sim}1.4{\mu}m$. Also, the height of ABL bumps was higher than I/O bumps. The degree of Cu bump planarization and Cu bump height uniformity within a die affected significantly on the misalignment and bonding quality of Cu-to-Cu flip chip bonding process. To utilize Cu-to-Cu flip chip bonding with ABL bumps, both bump planarization and within-die bump height control are required.

Flip Chip Process on the Local Stiffness-variant Stretchable Substrate for Stretchable Electronic Packages (신축성 전자패키지용 강성도 국부변환 신축기판에서의 플립칩 공정)

  • Park, Donghyeun;Oh, Tae Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.4
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    • pp.155-161
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    • 2018
  • A Si chip with the Cu/Au bumps of $100-{\mu}m$ diameter was flip-chip bonded using different anisotropic conductive adhesives (ACAs) onto the local stiffness-variant stretchable substrate consisting of polydimethylsiloxane (PDMS) and flexible printed circuit board (FPCB). The average contact resistances of the flip-chip joints processed with ACAs containing different conductive particles were evaluated and compared. The specimen, which was flip-chip bonded using the ACA with Au-coated polymer balls as conductive particles, exhibited a contact resistance of $43.2m{\Omega}$. The contact resistance of the Si chip, which was flip-chip processed with the ACA containing SnBi solder particles, was measured as $36.2m{\Omega}$, On the contrary, an electric open occurred for the sample bonded using the ACA with Ni particles, which was attributed to the formation of flip-chip joints without any entrapped Ni particles because of the least amount of Ni particles in the ACA.

Electromigration Behavior of the Flip-Chip Bonded Sn-3.5Ag-0.5Cu Solder Bumps (플립칩 본딩된 Sn-3.5Ag-0.5Cu 솔더범프의 electromigration 거동)

  • Choi Jae-Hoon;Jun Sung-Woo;Won Hae-Jin;Jung Boo-Yang;Oh Tae-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.11 no.4 s.33
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    • pp.43-48
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    • 2004
  • Electromigration of Sn-3.5Ag-0.5Cu solder bumps was investigated with current densities of $3{\~}4{\times}10^4 A/cm^2$ at temperatures of $130{\~}160^{\circ}C$ using flip chip specimens which consisted of upper Si chip and lower Si substrate. Electromigration failure of the Sn-3.5Ag-0.5Cu solder bump occurred with complete consumption of Cu UBM and void formation at cathode side of the solder bump. The activation energies for electromigration of the Sn-3.5Ag-0.5Cu solder bump were measured as 0.61 eV at current density of $3{\times}10^4 A/cm^2$, 0.63 eV at $3.5{\times}10^4 A/cm^2$, and 0.77 eV at $4{\times}10^4 A/cm^2$, respectively.

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Contact Resistance of the Flip-Chip Joints Processed with Cu Mushroom Bumps (Cu 머쉬룸 범프를 적용한 플립칩 접속부의 접속저항)

  • Park, Sun-Hee;Oh, Tae-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.3
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    • pp.9-17
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    • 2008
  • Cu mushroom bumps were formed by electrodeposition and flip-chip bonded to Sn substrate pads. Contact resistances of the Cu-mushroom-bump joints were measured and compared with those of the Sn-planar-bump joints. The Cu-mushroom-bump joints, processed at bonding stresses ranging from 19.1 to 95.2 MPa, exhibited contact resistances near $15m\Omega$/bump. Superior contact-resistance characteristics to those of the Sn-planar-bump joints were obtained with the Cu-mushroom-bump joints. Contact resistance of the Cu-mushroom-bump joints was not dependent upon the thickness of the as-elecroplated Sn-capcoating layer ranging from $1{\mu}m$ to $4{\mu}m$. When the Sn-cap-coating layer was reflowed, however, the contact resistance was greatly affected by the thickness and the reflow time of the Sn-cap-coating layer.

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Flip Chip Process for RF Packages Using Joint Structures of Cu and Sn Bumps (Cu 범프와 Sn 범프의 접속구조를 이용한 RF 패키지용 플립칩 공정)

  • Choi, J.Y.;Kim, M.Y.;Lim, S.K.;Oh, T.S.
    • Journal of the Microelectronics and Packaging Society
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    • v.16 no.3
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    • pp.67-73
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    • 2009
  • Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

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Microstructure and Contact Resistance of the Au-Sn Flip-Chip Joints Processed by Electrodeposition (전기도금법을 이용하여 형성한 Au-Sn 플립칩 접속부의 미세구조 및 접속저항)

  • Kim, S.K.;Oh, T.S.
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.4
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    • pp.9-15
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    • 2008
  • Microstructure and contact resistance of the Au-Sn solder joints were characterized after flip-chip bonding of the Au/Sn bumps processed by successive electrodeposition of Au and Sn. Microstructure of the Au-Sn solder joints, formed by flip-chip bonding at $285^{\circ}C$ for 30 sec, was composed of the $Au_5Sn$+AuSn lamellar structure. The interlamellar spacing of the $Au_5Sn$+AuSn structure increased by reflowing at $310^{\circ}C$ for 3 min after flip-chip bonding. While the Au-Sn solder joints formed by flip-chip bonding at $285^{\circ}C$ for 30 sec exhibited an average contact resistance of 15.6 $m{\Omega}$/bump, the Au-Sn solder joints reflowed at $310^{\circ}C$ for 3 min after flip-chip bonding possessed an average contact resistance of 15.0 $m{\Omega}$/bump.

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