• 한국신재생에너지학회:학술대회논문집
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• 2007.06a
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• pp.243-243
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• 2007

• Proceedings of the Korean Vacuum Society Conference
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• 2004.08a
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• pp.171-171
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• 2004

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1345-1346
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• 2007

다양한 게이트 절연막의 펜타신 박막 트랜지스터의 전기적 특성을 atomic force microscope (AFM), X-선 회절을 사용하여 분석하였다. 펜타신 박막 트랜지스터는 thermal evaporator 방법을 사용하여 여러 폴리며 기판위에 제작하였다. Hexamethylsilasane (HMDS), polyvinyl acetate (PVA), polymethyl methacrylate (PMMA)등의 폴리머 기판을 사용하여 다양한 온도에서 증착시켰다. 이 때 PMMA위에 증착시킨 펜타신의 경우가 가장 큰 그레인 크기를 보였고, 가장 적은 트랩 농도를 보였다. 그리고 상부 전극 구조를 가진 박막 트랜지스터를 HMDS 처리를 한 $SiO_2$와 PMMA 절연막을 사용하여 제작하고 비교하였다. 이때 PMMA기판 위에 제작한 트랜지스터는 전계효과 이동도가 ${\mu}_{FET}=0.03cm^{2}/Vs$ 이고, 문턱이전 기울기 0.55V/dec, 문턱전압 $V_{th}=-6V$, on/off 전류비 $>10^5$의 전기적 특성을 보였고, $SiO_2$ 기판위에 제작한 트랜지스터는 전계효과 이동도 ${\mu}_{FET}=0.004cm^{2}/Vs$, 문턱이전 기울기 0.518 V/dec, 문턱전압 $V_{th}=5V$, on/off 전류비 $>10^4$의 전기적 특성을 보였다.

• Journal of the Korean Vacuum Society
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• v.17 no.5
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• pp.394-399
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• 2008

Growth and electronic structure of pentacene film on silicon oxide before and after octadecyltrichlorosilane (OTS) treatment have been studied by photoelectron spectroscopy and photoelectron emission microscopy. On the OTS-treated surface, due to the weak interaction between the substrate and pentacene, the diffusion of pentacene is enhanced and domain size gradually grows, leading to a gradual change of the HOMO offset position. On the bare silicon oxide, the change of the HOMO position is marginal because of relatively strong interaction between the substrate and pentacene from the beginning.

• Journal of the Korean Vacuum Society
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• v.20 no.1
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• pp.63-69
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• 2011

In this study, we report on the novel lithographic patterning method to fabricate organic thin film field effect transistors (OTFTs) based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30 nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce $Al_2O_3$ film grown via atomic layer deposition method onto pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated micron sized pentacene FETs and measured their electrical characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.3
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• pp.177-182
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• 2010

The pentacene-based organic thin film transistors(OTFTs) using polyvinylalcohol(PVA) alignment layer were fabricated on the $SiO_2$ evaporated to n-type (111) Si substrates. The pentacene film was deposited by thermally evaporated at $10^{-7}$ torr. X-ray diffraction (XRD) and atomic force microscope(AFM) measurement showed pentacene film which deposited on rubbed PVA layers were partially crystallized at (001) plane. The pentacene OTFTs with PVA layers rubbed perpendicular to the direction of current flow was shown to align better orientation than parallel rubbed case and thus to enhance the mobility and saturation current by a factor of 2.3 respectively. We obtained mobility by 0.026 $cm^2$/Vs and on-off current ratio by ${\sim}10^8$.

• Journal of the Korean Vacuum Society
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• v.18 no.2
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• pp.147-150
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• 2009

We present a technique for fabricating low leakage organic field-effect transistors by a functional polydimethylsiloxane (PDMS) layer. The technique relies on the photo-chemical process of conversion of the PDMS to a silicon oxide which provides the selective growth of pentacene thin films. The reduced gate leakage current showed ${\sim}10^{-10}$ A in a linear ($V_d=-5\;V$) and saturation ($V_d=-30\;V$) region at $V_g-V_t>0$.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1277-1278
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• 2008

Pentacene 박막 트랜지스터의 소스/드레인 전극을 폴리머인 Poly(3,4-ethylene dioxythiophene) poly(styrenesulfonate) (PEDOT:PSS)를 사용하여 잉크젯 프린팅 방법으로 제작하였다. 펜타신 박막 트랜지스터는 열 증착법을 사용하여 폴리며 기판위에 100nm의 두께로 증착하였다. 게이트 절연막은 $SiO_2$ 위에 Polymethly Methacrylate (PMMA)를 증착시킨 double layer를 사용하였다. PMMA 위에 증착시킨 pentacene 결정립이 $SiO_2$ 위에 증착한 pentacene 결정립 보다 크게 성장하였고, double layer의 절연막을 씀으로 인해 게이트 누설 전류가 감소함을 보였다. Pentacene 증착 온도에 따른 결정립 크기를 비교하여 가장 적절한 온도를 찾았다. 프린팅 방법을 사용하여 만든 박막 트랜지스터는 전계효과 이동도가 ${\mu}_{FET}=0.023cm^2/Vs$ 이고, 문턱이전 기울기 S.S=0.49V/dec, 문턱전압 $V_{th}=-18V$, $I_{on}/I_{off}$ 전류비 >$10^3$의 전기적 특성을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.18-22
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• 2006

The inspection of surface properties under n-octadecyltrichlorosilane treated $SiO_2$ film was carried out by current-voltage characteristic and the scanning electron microscope. The voltage at zero current in low electric field is the lowest at 0.3 % OTS treated $SiO_2$ film with hybrid type. $SiO_2$ films changed from inorganic to hybrid or organic properties according to the increase of OTS content. OTS treated $SiO_2$ films with hybrid properties decreased the leakage currents, and the grain size of pentacene deposited sample was also the most small at the hybrid properties. The perpendicular generation of pentacene molecular was related with the surface of insulators. The surface with hybrid properties decreased the grain size, but that with inorganic or organic properties increased the grain size.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.80-83
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• 2000

In this work we deposited Pentacene thin film by OMBD at the various substrate temperatures, deposition rate and the various annealing temperatures for the fabrication of organic TFT and investigated the electrical and film surface characteristics such as sheet resistance, contact resistance and conductance Film thickness were measured by $\alpha$-step and the sheet resistance, contact resistance and conductance were extracted from the relation between the distance of the contacts and the resistance. During the film deposition the substrate temperature was held at 3$0^{\circ}C$, 4$0^{\circ}C$, 5$0^{\circ}C$, 6$0^{\circ}C$, 8$0^{\circ}C$ and 10$0^{\circ}C$, respectively. After the film deposition, Au contact was deposited by thermal evaporation. For the effect of annealing, the thin film was annealed in the nitrogen environment at 10$0^{\circ}C$ and 14$0^{\circ}C$ for 10 seconds, respectively. Film surface characteristics at the vatious substrate temperatures were measured by AFM. The crystallization of thin film was improved as the substrate temperatures were increased and the maximum gram size was 4${\mu}{\textrm}{m}$. The conductivity of thin film was found to be 7.40 $\times$10$^{-7}$ ~ 7.78$\times$10$^{-6}$ S/cm and the minimum contact resistance was 2.5324 ㏁.