• Transactions of the Korean Society of Automotive Engineers
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• v.21 no.6
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• pp.49-57
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• 2013

In this study, we fabricated a parallelly connected Li-ion battery/supercapacitor hybrid cell to combine the advantageous characteristics of Li-ion battery and supercapacitor, high energy density and high power density, respectively, and investigated its discharging characteristics over a wide temperature range from -40 to $25^{\circ}C$. At the initial state of discharging of the hybrid cell, the power was mostly provided by the supercapacitor and then the portion of the Li-ion battery was gradually increased. By installing a switching system into the hybrid cell, which controls the discharging sequence of Li-ion battery and supercapacitor, the maximum power was improved by 40% compared with non switching system. In addition at low temperatures, the power and discharging time of the hybrid cell were significantly enhanced compared to a battery-alone system. The hybrid cell is expected to be applied in electric vehicles and small domestic appliances that require high power at initial discharging state.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.12-12
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• 2011

최근 휴대용 전자기기의 사용이 증가함에 따라 비휘발성 메모리 소자에 대한 수요가 급증하고 있다. 다양한 메모리 소자 중에서 현재는 플래시 메모리를 기반으로 하는 비휘발성 메모리 소자의 연구 및 개발이 활발히 이루어지고 있으며, 플래시 메모리 소자의 경우 모든 반도체 메모리 소자 중에서 가장 빠른 발전 속도로 개발되고 있다. 이러한 플래시 메모리 소자의 발전을 기반으로 스마트폰, 디지털 카메라, 태블릿 PC 등의 개발 및 대중화를 가져왔다. 이러한 플래시 메모리를 기반으로 하는 비휘발성 메모리 소자의 경우 반도체 소자의 발전을 주도하며 발전하고 있으나, 새로운 전자기기 및 소자(flexible electronics, printed electronics, organic electronics 등) 응용을 위해서는 저비용으로 쉽게 제작할 수 있는 메모리 소자의 개발이 필요하다. 이에 적합한 메모리 소자 구조는 기존 플래시 메모리 소자와 유사한 트랜지스터 기반의 메모리 소자라고 할 수 있다. 본 발표에서는 플래시 메모리 소자와 유사한 구조 및 동작 특성을 갖는 자기조립된 금속나노입자를 정보저장층으로 이용하는 비휘발성 메모리 소자 개발에 대한 내용을 소개하고자 한다. MOS 캐패시터나 박막트랜지스터 내의 게이트 절연층에 자기조립된 금속 나노입자를 삽입하여 비휘발성 메모리 소자를 구현하였다. 게이트에 인가되는 전압에 따라 금속 나노입자 층에 전하를 trap/detrap 시킬 수 있으며, 이러한 거동에 따라 MOS 캐패시터 또는 트랜지스터 구조의 메모리 소자의 문턱전압 값이 변화하게 되어 program/erase 상태를 확인할 수 있다. 실리콘 게이트를 이용하는 메모리 소자, 다층의 정보저장층을 이용하는 메모리 소자, 프린팅 공정에 의해 형성된 메모리 소자 등 다양한 형태의 나노입자 기반 메모리 소자를 구현하였으며, 이러한 나노입자 기반 비휘발성 메모리 소자의 경우, 우수한 동작 특성 및 향상된 신뢰성을 보여주어, 차세대 메모리 소자로 이용하기에 적합한 특성을 나타내었다. 또한 대부분의 공정이 저온에서 가능하기 때문에 최종적인 메모리 소자의 플랫폼으로 플렉서블 플라스틱 기판을 이용하여, 유기트랜지스터 기반의 플렉서블 메모리 소자를 구현하였다. 본 발표에서는 다양한 형태의 나노입자 기반 비휘발성 메모리 소자의 제작 방법, 동작 특성, 신뢰성 평가 등에 대해 자세히 논의될 것이다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.2
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• pp.211-217
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• 2015

Emission gas regulations and constantly increasing fuel costs call for the worldwide use of environmentally friendly and energy-efficient machines in industry. To meet these requirements, a hybrid excavator prototype has been developed that incorporates an electric swing motor, engine assist motor, and ultra-capacitor module into a conventional hydraulic excavator of the 22-ton class. This paper mainly describes a few techniques to optimize its energy efficiency. These include 1) controlling the engine speed in proportion to the load torque, 2) controlling the pump displacement when driving the electric swing system, 3) managing the ultra-capacitor voltage to minimize the electrical energy loss, and 4) reducing the cooling fan speed to improve the energy efficiency of the system.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.5
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• pp.43-50
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• 2002

To improve the current waveform of diode rectifiers, we propose a new operating principle for the voltage -doubler diode rectifiers. In the conventional voltage-doubler rectifier circuit, relatively large capacitors are used to boost the output voltage, while the proposed circuit uses smaller ones and a small reactor not to boost the output voltage but improve the input current waveform. A high input power factor of 97[%] and an efficiency of 98[%] are also obtained. The harmonic guide lines of proposed rectifier is no interfered with inverter switching, resulting in a simple, reliable and low-cost ac-to dc converters in comparison with the boost-type current-improving circuits.It compared conventional pulse-widthmodulated(PWM)inverter with half pulse-widthmodulated (HPWM) inverter. Proposed HPWM inverter eliminated dead-time by lowering switchingloss and holding over-shooting.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.83-90
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• 1998

The effects of dopant activation anneal on GOI (Gate Oxide Integrity) of MOS capacitor with amorphous silicon gate electrode were investigated. It was found that the amorphous silicon gate electrode was crystallized and the dopant atoms were sufficiently activated by activation anneal. The mechanical stress of gate electrode that reveals large compressive stress in amorphous state, was released with increase of anneal temperature from $700^{\circ}C$ to 90$0^{\circ}C$. The resistivity of gate electrode polycrystalline silicon film is decreased by the increase of anneal temperature. The reliability of thin gate oxide and interface properties between oxide and silicon substrate greatly depends on the activation anneal temperature. The charge trapping characteristics as well as oxide reliability are improved by the anneal of 90$0^{\circ}C$ compare to that of $700^{\circ}C$ or 80$0^{\circ}C$. Especially, the lifetimes of the thin gate oxide estimated by TDDB method is 3$\times$10$^{10}$ for the case of $700^{\circ}C$ anneal, is significantly increased to 2$\times$10$^{12}$ for the case of 90$0^{\circ}C$ anneal. Finally, the interface trap density is reduced with relaxation of mechanical stress of gate electrode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.58-65
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• 2009

In this paper, we designed high voltage gate drive IC including dead time circuit in which capacitors controlled rising time and falling time, and schimitt-triggers controlled switching voltage. Designed High voltage gate drive IC improves an efficiency of half-bridge converter by decreasing dead time variation against temperature and has variable dead time by the capacitor value. and its power dissipation, which is generated on high side part level shifter, has decreased 52 percent by short pulse generation circuit, and UVLO circuit is designed to prevent false-operation. We simulated by using Spectre of Cadence to verify the proposed circuit and fabricated in a 1.0um process.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.88-88
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• 2018

DLC(Diamond Like Carbon) 박막은 높은 열전도도, 큰 전기저항, 높은 강도 등의 다이아몬드와 유사한 특성을 가지고 있으면서 저온 저압에서도 합성이 가능하고, 합성 조건에 따라 물리 화학적 특성도 넓게 조절 할 수 있으며 상대적으로 넓은 면적에서 균일하고 평활한 박막의 합성이 가능하여 산업적 응용 면에서도 경쟁력을 갖추고 있다[1]. 이러한 DLC 박막을 합성함에 있어서 RF-PECVD(Radio Frequency Plasma Enhanced Chemical Vapor Deposition) 방법은 PECVD 방법 중 가장 보편적으로 사용되고 또 캐패시터 타입의 RF-PECVD 방법은 균일한 대면적 증착과 대량생산이 가능하다[1,2]. 본 연구에서는 우수한 특성을 갖는 DLC 박막의 증착 조건을 찾기 위해 캐패시터 타입의 RF-PECVD를 사용하여 공정 가스의 유량과 RF Power를 변화하여 박막을 증착하고, 증착된 박막의 특성을 연구하였다. DLC 박막은 ITO(Indium Tin Oxide) 유리 기판 위에 $100^{\circ}C$에서 5 min 동안 아세틸렌($C_2H_2$) 가스를 사용하여 가스 유량과 RF Power를 변화하여 증착하였다. 증착된 DLC 박막의 특성은 투과도, 평탄도, 두께를 측정하여 비교하였다. 가시광선 영역(380-780 nm)에서 투과도를 측정한 결과 ITO 유리 기판을 기준으로 한 DLC 박막의 투과도는 가시광선 영역 평균 94.8~98.8% 사이의 값으로 매우 높은 투과율을 나타내었다. 투과도는 가스 유량이 증가함에 따라 증가하는 경향을 나타내었고, RF Power의 변화에는 특정한 변화를 나타내지 않았다. 박막의 평탄도($R_a$, $R_{rms}$)와 두께는 AFM(Atomic Force Microscope)을 사용하여 측정하였다. 평탄도 $R_{rms}$는 0.8~3.3 nm, $R_a$는 0.6~2.5 nm 사이를 나타내었고 RF Power와 가스 유량의 변화에 따른 경향성을 나타내지는 않았다. 두께는 RF Power 25 W에서 55 W로 증가함에 따라 증가하는 경향을 나타내었으나 70W에서는 가스의 유량에 따라 상이한 결과를 나타내었다.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.1
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• pp.27-31
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• 2007

The cpapcitors with MIM(metal-insulator-metal) structures using PVP gate insulation films were prepared for the application of flexible organic thin film transistors (OTFT). The co-polymer organic insulation films were synthesized by using PVP(poly-4-vinylphenol) as a solute and PGMEA(propylene glycol monomethyl ether acetate) as a solvent. The cross-linked PVP insulation films were also prepared by addition of poly(melamine-co-formaldehyde) as thermal hardener. The leakage current of the cross- linked PVP films was found to be about 1.3 nA on Al/PES(polyethersulfone) substrate, whereas, on ITO/ glass substrate was about 27.5 nA indicating improvement of the leakage current at Al/PES substrates. Also, the capacitances of all prepared samples on ITO/glass and Al/PES substrates w ere ranged from 1.0 to $1.2nF/cm^2$, showing very similar result with the calculated capacitance values.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.312-320
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• 2003

This work describes an 8b 200 MHz 0.18 urn CMOS analog-to-digital converter (ADC) based on a pipelined architecture for flat panel display applications. The proposed ABC employs an improved bootstrapping technique to obtain wider input bandwidth than the sampling tate of 200 MHz. The bootstrapuing technique improves the accuracy of the input sample-and-hold amplifier (SHA) and the fast fourier transform (FFT) analysis of the SHA outputs shows the 7.2 effective number of bits with an input sinusoidal wave frequency of 500 MHz and the sampling clock of 200 MHz at a 1.7 V supply voltage. Merged-capacitor switching (MCS) technique increases the sampling rate of the ADC by reducing the number of capacitors required in conventional ADC's by 50 % and minimizes chip area simultaneously. The simulated ADC in a 0.18 um n-well single-poly quad-metal CMOS technology shows an 8b resolution and a 73 mW power dissipation at a 200 MHz sampling clock and a 1.7 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.23-29
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• 2012

The LC-based digitally controlled oscillator (LC-DCO), a key component of the all digital phase locked loop (ADPLL), is designed using $0.18{\mu}m$ RFCMOS process with 1.8 V supply. The NMOS core with double cross-coupled pair is chosen to realize wide tuning range, and the PMOS varactor pair that has small capacitance of a few aF and the capacitive degeneration technique to shrink the capacitive element are adopted to obtain the high frequency resolution. Also, the noise filtering technique is used to improve phase noise performance. Measurement results show the center frequency of 2.7 GHz, the tuning range of 2.5 GHz and the high frequency resolution of 2.9 kHz ~7.1 kHz. Also the fine tuning range and the current consumption of the core could be controlled by using the array of PMOS transistors using current biasing. The current consumption is between 17 mA and 26 mA at 1.8V supply voltage. The proposed DCO could be used widely in various communication system.