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A Design of 1.42 - 3.97GHz Digitally Controlled LC Oscillator  

Lee, Jong-Suk (School of Electronic Engineering, Soongsil University)
Moon, Yong (School of Electronic Engineering, Soongsil University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.49, no.7, 2012 , pp. 23-29 More about this Journal
Abstract
The LC-based digitally controlled oscillator (LC-DCO), a key component of the all digital phase locked loop (ADPLL), is designed using $0.18{\mu}m$ RFCMOS process with 1.8 V supply. The NMOS core with double cross-coupled pair is chosen to realize wide tuning range, and the PMOS varactor pair that has small capacitance of a few aF and the capacitive degeneration technique to shrink the capacitive element are adopted to obtain the high frequency resolution. Also, the noise filtering technique is used to improve phase noise performance. Measurement results show the center frequency of 2.7 GHz, the tuning range of 2.5 GHz and the high frequency resolution of 2.9 kHz ~7.1 kHz. Also the fine tuning range and the current consumption of the core could be controlled by using the array of PMOS transistors using current biasing. The current consumption is between 17 mA and 26 mA at 1.8V supply voltage. The proposed DCO could be used widely in various communication system.
Keywords
PLL(Phase Locked Loop); ADPLL(All Digital PLL); DCO(Digitally Controlled Oscillator); Varactor; phase noise; biasing;
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