• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.12
• /
• pp.37-43
• /
• 2009

This paper describes a monolithic Darlington-cascade amplifier (DCA) operating at X-band, realized with a 0.35-micron SiGe bipolar process, which provides 45 GHz $f_T$. A conventional cascade amplifier was also designed on the same process and tested to establish a reference. Compared to the reference cascade amplifier, the proposed monolithic amplifier circuit exhibits an improved gain of 2.5 dB and improved output power 1-dB compression point of 5.2 dB with 72% wider bandwidth. Measurement results show 19.5 dB gain, 11.2 dBm 1-dB compression power, and 3.1 GHz bandwidth. These results demonstrate that the Darlington-cascade cell is an advantageous substitute to the conventional cascade amplifier.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.10
• /
• pp.1477-1483
• /
• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.7
• /
• pp.993-1000
• /
• 2018

This paper proposes a low-dropout voltage regulator(LDO) using self-cascode structure. The self-cascode structure was optimized by adjusting the channel length of the source-side MOSFET and applying a forward voltage to the body of the drain-side MOSFET. The self-cascode of the input differential stage of the error amplifier is optimized to give higher transconductance, but the self-cascode of the output stage is optimized to give higher output resistance, The proposed LDO using self-cascode structure was designed by a $0.18{\mu}m$ CMOS technology and simulated using SPECTRE. The load regulation of the proposed LDO regulator was 0.03V/A, whereas that of the conventional LDO was 0.29V/A. The line regulation of the proposed LDO regulator was 2.23mV/V, which is approximately three times improvement compared to that of the conventional LDO. The transient response of the proposed LDO regulator was 625ns, which is 346ns faster than that of the conventional LDO.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.1
• /
• pp.720-725
• /
• 2015

This paper describes the design of a wideband cascode amplifier using a feedback network and microwave small-signal transistors. The adopted cascode structure enables the miller effect to be lessened, cutoff frequency to increase, and reduction of gain in the mid-band to be mitigated. In addition, a feedback network is added to the cascode structure to improve the input matching and ripple performances over the wide operating band. The designed cascode amplifier contains a feedback network for small size and broadband amplification, whereas balanced amplifiers and distributed amplifiers have been used widely. The measurement shows $8.5dB{\pm}1.5dB$ of gain over 1000-2000MHz. The fabricated cascode amplifier has more than 8dB of gain over a 1000MHz bandwidth with a good flatness. The measured performances agree with the predicted ones even a minor shift in operating frequency is observed.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.469-471
• /
• 2008

The charge pump affects the performance of PLL. In designing the charge pump, we need to consider various issues such as current mismatch, charge sharing, feedthrough, charge injection, and leakage current. This paper propose the new charge pump circuit which is improved in terms of the current match over the existing high-speed charge pump. The simple method used for reducing current mismatch is the technique that uses a cascode in order to increase the output resistance of the charge pump. However the method limits the output voltage range of the charge pump. So the method is hard to apply as the supply voltage is lowered. Thus this paper proposes a new charge pump circuit using an op amp instead of the cascode. And the new charge pump circuit has an excellent current matching characteristics over a wide output range.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.3
• /
• pp.647-653
• /
• 2005

According to the design concept of microwave front-end, a low noise amplifier block using HBT cascode topology is proposed to provide high gain and low noise figure with low bias current. We has implemented MMIC-LNA with a modified configuration using inductors to show low noise at the emitter and base of cascoded HBT-MMIC amplifier. The measured performance of the designed MMIC-LNA at 3.7GHz are a gain of 19dB, noise figure of 2.7dB and image rejection of 35dBc using a supply of 3mA and 2.7V. We can convinced that cascoded amplifier block to fulfill a high gain, low noise and image rejection if microwave front-end receiver is designed by cascode MMEC-LNA with the active image rejection filter.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.4
• /
• pp.277-282
• /
• 2020

This study was initiated to find a way to resolve electronic equipment as it could be affected by multiple environments. The effect of setting the exponential constant wave (iExp) in the telescopic cascade comparator to the SET (Single Event Transient) environment was tested. In this paper, the radio wave delay was measured at 0.46 ㎲ and the gain at 0.713 in the telescopic cascade comparator without setting the SET situation. FET T0 (M6) was measured to have a large spike at 11㎲ to 15㎲ in the telescopic cascade comparator entering the SET situation. FET T1 (M5) has shorted output signals from 10 ㎲ to 16 ㎲. FET T2 (M3) represented a shorted output signal, and FET T3 (M4) measured the output waveform in the form of a large spike waveform. The FET T4 (M1) and FET T5 (M2) are spiky signals. And at all FETs, the propagation delay was changed from 0.45㎲ to 0.54㎲. In summary, The FET element in the telescopic cascade comparator in SET situation was measured to be greatly affected.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1992.10a
• /
• pp.317-322
• /
• 1992

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.2
• /
• pp.345-352
• /
• 2017

In this paper, a unified potentiostat which can measure the current of both $O_2$-based and $H_2O_2$-based blood glucose sensors with low supply voltage of 1.0V has been designed and verified by simulations and measurements. Potentiostat is composed of low-voltage operational transconductance amplifier, cascode current mirrors and mode-selection circuits. It can measure currents of blood glucose chemical reactions occurred by $O_2$ or $H_2O_2$. The body of PMOS input differentional stage of the operational transconductance amplifier is forward-biased to reduce the threshold voltage for low supply voltage operation. Also, cascode current mirror is used to reduce current measurement error generated by channel length modulation effects. The proposed low-voltage potentiostat is designed and simulated using Cadence SPECTRE and fabricated in Magnachip 0.18um CMOS technology with chip size of $110{\mu}m{\times}60{\mu}m$. The measurement results show that consumption current is maximum $46{\mu}A$ at supply voltage of 1.0V. Using the persian potassium($K_3Fe(CN)_6$) equivalent to glucose, the operation of the fabricated potentiostat was confirmed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.1
• /
• pp.106-113
• /
• 2003

In this paper, we proposed low noise amplifier for 2.4GHz ISM frequency with CMOS technology. The property of noise and gain is improved by cascode architecture. The architecture, which common source output of cascode is connected to input of parallel MOS, reduce IM. The LNA results based on Hynix 0.35${\mu}{\textrm}{m}$ 2poly 4metal CMOS processor with a 3.3V supply. It achieves a gain of 13dB, noise figure of 1.7dB, IP3 of 8dBm, Input/output matching of -31dB/-28dB, reverse isolation of -25dB. and power dissipation of 4.7mW with HSPICE simulation. The size of layout is smaller than 2 ${\times}$ 2mm with Mentor.