• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.632-638
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• 2011

This paper presents on-chip Design-for-Testability (DFT) circuit for radio frequency System-on-Chip (SoC) applications. The proposed circuit measures functional specifications of RF integrated circuits such as input impedance, gain, noise figure, input voltage standing wave ratio (VSWRin) and output signal-to-noise ratio (SNRout) without any expensive external equipment. The RF DFT scheme is based on developed theoretical expressions that produce the actual RF device specifications by output DC voltages from the DFT chip. The proposed DFT showed deviation of less than 2% as compared to expensive external equipment measurement. It is expected that this circuit can save marginally failing chips in the production testing as well as in the RF system; hence, saving tremendous amount of revenue for unnecessary device replacements.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.20-26
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• 2016

This paper presents an X-band two-stage power amplifier using GaN-HEMT. Two-stage structure was adopted to take its high gain and simple inter-stage matching network. Based on a 3D EM simulation, the bond-wire inductance and the parasitic capacitance were predicted. By reducing bond-wire inductance, Q of the matching network is decreased and the bandwidth is improved. The implemented two-stage PA shows a power gain of more than 16 dB, saturated output power of more than 42.5 dBm, and a efficiency of more than 35 % in frequency range of 8.1~8.5 GHz with an operating voltage of 40 V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1429-1435
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• 2004

In this work, high performance broadband amplifier MMIC including all the matching and biasing components, and electrostatic discharge (ESD) protection circuit was developed for K/Ka band applications. Therefore, external biasing or matching components were not required for the operation of the MMIC. STO (SrTiO3) capacitors were employed to integrate the DC biasing components on the MMIC, and miniaturized LC parallel ESD protection circuit was integrated on MMIC, which increased ESD breakdown voltage from 10 to 300 V. A pre-matching technique and RC parallel circuit were used for the broadband design of the amplifier MMIC. The amplifier MMIC exhibited good RF performances and good stability in a wide frequency range. The chip size of the MMICs was $1.7{\pm}0.8$ mm2.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.4
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• pp.67-72
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• 2022

This study presents the design of power amplifier (PA) in 60 nm GaN/Si HEMT technology. A customized transistor model enables the designing circuits operating at W-band. The all matching network of the PA was composed of equivalent transformer circuit to reduce matching loss. And then, equivalent transformer is several advantages without any additional inductive devices so that a wideband power characteristic can be achieved. The designed die area is 3900 ㎛ × 2300 ㎛. The designed results at center frequency achieved the small signal gain of 15.9 dB, the saturated output power (Psat) of 29.9 dBm, and the power added efficiency (PAE) of 24.2% at the supply voltage of 12 V.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.755-758
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• 2003

본 논문에서 단거리전용통신(DSRC)용 OBE에 사용되는 5.8GHz 송신측 ASK와 PA를 one-chip화하여 MMIC로 설계를 및 제작하였다. 설계된 ASK-PA는 3V 단일 공급전원을 사용하였고, 능동 소자로서 GaAs MESFET을 사용하였다. ASK는 회로의 복잡도를 줄이기 위해 직접변조 방식을 채택하였고, 인접채널 간섭의 영향을 줄이기 위하여 드레인 제어 변조회로를 사용하였다. 또한 전력증폭기는 2단으로 하여 AB급으로 동작하도록 전압분배 바이어스회로로 구성하였다. 측정결과 3V의 공급전압에서 전체이득 20.63dB, 송신출력 7.8dBm으로 나타냈다. 공정은 ETRI 0.5㎛ GaAs MESFET 공정을 사용하였고, Chip size는 1.2mm×l.4mm이다.

• Journal of IKEEE
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• v.18 no.4
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• pp.586-592
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• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.97-105
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• 2016

Radiography image detector produces digital images by collecting the charges from the incident x-ray photons and converting it to the voltage signals and then the digital signals. The fixed-pattern noise from the nonuinform amplifier gains in the employed multiple readout circuits. In order to correct the nonuniform gains, a gain-correction technique which is based on the gain map is conventionally used. Since the photon noise remains in the designed gain map, the noise contaminates the gain-corrected images. In this paper, experimental observations are conducted for filtering the remained noise in the gain map, and a filter optimization algorithm is proposed to efficiently remove the noise. For acquired x-ray images from detectors, the filtered gain maps are evaluated and it is shown that optimization algorithm can improve the filtering performance even for relatively strong fixed-pattern noises, which cannot be removed by a simple filter.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1526-1531
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• 2009

This paper describes the design of a 5th order Elliptic CMOS Gm-C low-voltage filter for the RFID reader IC. The designed filter is composed of CMOS differential transconductors by parallel gain circuits to improve the gain of the conventional self-biased differential amplifier. The filter is designed to operate in low-voltage 1.8V to meet the specification of the RFID reader filter. The results of HSPICE simulation using 1.8V-0.18${\mu}m$CMOS processing parameter showed that the designed 5th order Elliptic low-pass filter satisfied the cutoff frequency of 1.35MHz given by the design specification.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.53-60
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• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.91-96
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• 2011

In this paper, a low-power direct-conversion transmitter based on current-mode operation, which satisfies the IEEE 802.15.4 standard, is proposed and implemented in a $0.13{\mu}m$ CMOS technology. The proposed transmitter consists of DACs, LPFs, variable gain I/Q up-conversion mixer, a divide-by-two circuit with LO buffer, and a drive amplifier. By combining DAC, LPF, and variable gain I/Q up-conversion mixer with a simple current mirror configuration, the transmitter's power consumption is reduced and its linearity is improved. The drive amplifier is a cascode amplifier with gain controls and the 2.4GHz I/Q differential LO signals are generated by a divide-by-two current-mode-logic (CML) circuit with an external 4.8GHz input signal. The implemented transmitter has 30dB of gain control range, 0dBm of maximum transmit output power, 33dBc of local oscillator leakage, and 40dBc of the transmit third harmonic component. The transmitter dissipates 10.2mW from a 1.2V supply and the die area of the transmitter is $1.76mm{\times}1.26mm$.