• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.89-96
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• 2004

High-linearity voltage-controlled current sources (VCCSs) circuits for wide voltage-controlled oscillator and automatic gain control are proposed. The VCCS consists of emitter follower for voltage input, two common-base amplifier which their emitter connected for current output, and current mirror which connected the two amplifier for large output current. The VCCS used only five transistors and a resistor without an extra bias circuit. Simulation results show that the VCCS has current output range from 0㎃ to 300㎃ over the control voltage range from 1V to 4.8V at supply voltage 5V. The linearity error of output current has less than 1.4% over the current range from 0A to 300㎃.

• Proceedings of the Optical Society of Korea Conference
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• 1995.06a
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• pp.149-153
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• 1995

세슘원자에 대한 레이저 쿨링용 광원으로 사용하기 위해 다이오드 레이저의 서폭을 축소하고 발진 주파수 및 출력을 동시에 안정화 시키는 연구를 수행하였다. 자유발진 상태에서 약 30 MHz 이고, 출력이 10mW인 다이오드 레이저에 유이창으로 Q 갑이 낮은 외부 공진기를 구성함으로써 발진선폭을 약 5MHz로 줄일수 있었다. 그리고 세슘원자의 포화흡수 스펙트럽의 교차공진 흡수선에 레이저 주파수를 안정시키기 위해 주입전류를 10kHz 로 변조하고, lock-in amp 의 출력단에서 나오는 주파수 오차신호를 전류공급장치와 유리창이 부착된 PZT로 동시에 피드백시켰다. 또한 오차신호를 레이저 다이오드의 온도 조절장치로 피드백 시킴으로써 주파수와 동시에 레이저 출력을 안정화시킬 수 있었다. 이 때의 출력의 변동폭은 약 0.03% 로서 온도로 피드백 시키지 않는 경우에 비해 약 260배 안정된 결과를 얻었다. 그리고 컴퓨터를 이용해서 흡수선의 peak 값을 매 10초마다 검색하고 이 값이 최대가 되도록 PZT 전압을 조절함으로써 레이저 주파수를 세슘원자의 흡수선의 봉우리에 1주일 이상 안정화시킬 수 있었다. 주파수 안정도 측정을 위해 Zeeman 이동된 포화흡수 스펙트로미터를 구성하였으며, 측정된 주파수 안정도 (Allan 분산의 제곱근)는 적분시간 1초 일 때 1.2x10-10 이었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.212-215
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• 2016

In this paper, a 5.08 GHz Ring Voltage Controlled Oscillator(Ring VCO) was implemented using $0.18{\mu}m$ standard CMOS technology. The proposal Ring VCO is 3-stage structure. This research confirmed that the each stage's different transistor size ratio influence the current change and alter power consumption consequentially. This circuit is formed to control the current thereby adding the Current Mirror and to tune the frequency by supplying control voltage. It has an 65.5 %(1.88~5.45 GHz) tuning range. The measured output power is -0.30 dBm. The phase noise is -87.50 dBc/Hz @1 MHz offset with operating frequency of 5.08 GHz fundamental frequency. The total power consumption of Ring VCO is 31.2 mW with 2.4 V supply voltage.

• Journal of IKEEE
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• v.28 no.3
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• pp.445-450
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• 2024

This paper presents a varactor-less voltage-controlled oscillator (VCO) at W-band (75-110 GHz) with a compact size in a 0.15-㎛ GaAs pHEMT technology. For varactor-less frequency tuning, an inductive tuning circuit is employed. An active inductor is realized by the common-gate stage with gate termination and shows a wide tuning range with a high quality factor (Q-factor) compared with the conventional varactor diode. Colpitts topology with source feedback is employed for the oscillation core of the VCO. The varactor-less VCO exhibits a measured tuning range of 5.8 % and peak output power of 5.7 dBm at 88 GHz while the 146 mW of dc power is dissipated. Due to compact layout design, the chip size is only 0.48 mm².

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1112-1119
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• 2006

In this paper, mutually coupled oscillator is employed to improve phase noise. Mutually coupled structure oscillator couples two oscillator's phase shifted output signals, that is fabricated using teflon board which has dielectric constant of 2.5 and Surface Mount Gallium Arsenide FET devices. And this paper proposed the structure to bias adjustment for the phase condition of mutually couples. When one oscillator has bias point of 4.4 V and 37 mA, it's output signal has phase noise characteristic of -96.37 dBc(@9305 MHz, offset frequency 100 KHz), -73.46 dBc(10 kHz). and After it's output signal mutually coupled the other's output signal that has bias point of 8.1 V and 69 mA, it has superior phase noise characteristic of -106.7 dBc(@9305 MHz, offset frequency 100 kHz), -81 dBc(10 kHz).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.5
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• pp.453-458
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• 2010

In this work, a 18 GHz divide-by-4 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in $0.13-{\mu}m$ Si RFCMOS technology. The free-running oscillation frequency is from 4.98 to 5.22 GHz and output power is about －30 dBm, consuming 33.4 mW with a 1.5 V supply voltage. At 0 dBm input power, the locking range is 3.5 GHz(17.75~21.25 GHz) and with varactor tuning, the operating range is increased up to 5.25 GHz(16.0~21.25 GHz). The fabricated chip size is $0.76\;mm{\times}0.57\;mm$ including DC and RF pad.

• Journal of Industrial Technology
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• v.29 no.B
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• pp.101-105
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• 2009

A 1.571GHz LC VCO with optimized spiral inductor for GPS receiver is designed in 130nm CMOS process. The phase noise of the VCO has been reduced the use of high Q inductor and on chip filter. It has phase noise of -91dBc/Hz, -111dBc/Hz, and -131dBc/Hz at 10kHz, 100kHz, and 1MHz offset frequencies from the carrier, respectively. This VCO consumes 2mA from a 0.6V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.941-947
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• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.