• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.16-21
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• 2007

CMOS variable gain amplifier (VGA) IC designs for the structure monitoring systems of the telemetries were developed. A three stage cascaded VGA using a differential amplifier and a linear-in-dB controller is presented. A proposed VGA is a modified version of a conventional VGA such that the gain is controlled in a linear-in-dB fashion through the current ratio. The proposed VGA circuit introduced in this paper has a dynamic range of 77 dB with 1.5 dB gain steps. It also achieved a gain error of less than 1.5 dB over 77 dB gain range. The VGA can operate up to 10MHz dissipating 13.8 mW from a single 1.8 V supply. The core area of the VGA fabricated in a Magnachip $0.18{\mu}m$ standard CMOS process was about $430{\mu}m{\times}350{\mu}m$. According to measurement results, we can verify that the proposed method is reasonable with regard to the enhancement of dynamic range and the better linear-in-dB characteristics.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.87-95
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• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

• Journal of the Korean Electrochemical Society
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• v.19 no.3
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• pp.114-121
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• 2016

This study investigates a CFD modeling of the charge-discharge behavior due to heat generation during charge-discharge cycles of a Li-ion secondary battery(LIB). Present LIB system adopted a current-density equation, heat and mass transfer governing equations upon the 1-dimensional system to the thickness direction for the rectangular pouch configuration. According to the 3-kinds of the charge-discharge current densities of 1C($17.5A/m^2$), 3C($52.5A/m^2$) and 5C($87.5A/m^2$) subject to a 3 V of cut-off voltage, a constant-temperature system at 298 K and three different heat generating systems were analyzed with comparison. Battery capacity decreases with increment of charge-discharge densities not only at the constant-temperature system but also at the heat-generating system. The time for charge-discharge cycles increases at the heat-generating system compare to the constant-temperature system. These trends are considered that the increase of temperature due to heat generation causes the decrement of equilibrium potential of electrodes and the increment of diffusivity of Li ions. Furthermore, cooling effects were discussed in order to control the influence of heat generation due to charge-discharge behavior of a Li-ion secondary battery.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.7
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• pp.635-645
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• 2016

In this paper, we showed the phase noise of voltage controlled oscillator(VCO) can be radically improved using FLL(Frequency Locked Loop). At first, a 5 GHz VCO is fabricated using a hair-pin resonator. The fabricated VCO shows a phase noise of -53.1 dBc/Hz at 1 kHz frequency offset. In order to improve the phase noise of the fabricated VCO, a FLL is constructed using the feedback loop that consists of the VCO, a frequency detector composed of 5 GHz resonator, loop-filter, and level shifter. The fabricated FLL is designed to oscillate at a frequency of 5 GHz, and its measured phase noise is about -120.6 dBc/Hz at 1 kHz offset frequency. As a result, the phase noise of VCO can be radically improved by about 67.5 dB applying FLL. In addition, the measured phase noise performance is close to that of crystal oscillator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.7
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• pp.771-777
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• 2008

In this paper, a frequency doubler using modified time-delay technique is proposed. A voltage controlled delay line (VCDL) in the proposed frequency doubler compensates the group delay time mismatching between input and delayed signal. With the group delay time matching and waveform shaping using the adjustable Schmitt triggers, the unwanted fundamental component($f_0$) and the higher order harmonics such as third and fourth are diminished excellently. In result, only the doubled frequency component($2f_0$) appears dominantly at the output port. The frequency doubler is designed at 1.15 GHz of $f_0$ and fabricated with TSMC $0.18\;{\mu}m$ CMOS process. The measured output power at $2f_0$ is 2.67 dBm when the input power is 0 dBm. The obtained suppression ratio of $f_0,\;3f_0$, and $4f_0$ to $2f_0$ are 43.65, 38.65 and 35.59 dB, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.52-60
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• 2010

In this paper, we propose a dynamic power management framework for multi-core systems. We reduced the power consumption of multi-core processors such as Intel Centrino Duo and ARM11 MPCore, which have been used at the consumer electronics and personal computer market. Each processor uses a different technique to save its power usage, but there is no embedded multi-core processor which has a precise power control mechanism such as dynamic voltage scaling technique. The proposed dynamic power management framework is suitable for smart phones which have an operating system to provide multi-processing capability. Basically, our framework follows an intuitive idea that reducing the power consumption of idle cores is the most effective way to save the overall power consumption of a multi-core processor. We could minimize the energy consumption used by idle cores with application-targeted policies that reflect the characteristics of active workloads. We defined some properties of an application to analyze the performance requirement in real time and automated the management process to verify the result quickly. We tested the proposed framework with popular processors such as Intel Centrino Duo and ARM11 MPCore, and were able to find that our framework dynamically reduced the power consumption of multi-core processors and satisfied the performance requirement of each program.

• Journal of Adhesion and Interface
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• v.21 no.3
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• pp.86-92
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• 2020

We confirmed the effects on the device performances and the charge injection characteristics of organic field-effect transistor (OFET) by selectively differently controlling the surface energies on the contact region of the substrate where the source/drain electrodes are located and the channel region between the two electrodes. When the surface energies of the channel and contact regions were kept low and increased, respectively, the field-effect mobility of the OFET devices was 0.063 ㎠/V·s, the contact resistance was 132.2 kΩ·cm, and the subthreshold swing was 0.6 V/dec. They are the results of twice and 30 times improvements compared to the pristine FET device, respectively. As the results of analyzing the interfacial trap density according to the channel length, a major reason of the improved device performances could be anticipated that the pi-pi overlapping direction of polymer semiconductor molecules and the charge injection pathway from electrode is coincided by selective surface treatment in the contact region, which finally induces the decreases of the charge trap density in the polymer semiconducting film. The selective surface treatment method for the contact region between the electrode and the polymer semiconductor used in this study has the potential to maximize the electrical performances of organic electronics by being utilized with various existing processes to lower the interface resistance.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.148-148
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• 1999

다이아몬드에 버금가는 높은 경도뿐만 아니라 높은 화학적 안정성 및 열전도성 등 우수한 물리화학적 특성을 가진 입방정 질화붕소(cubic Boron Nitride)는 마찰.마모, 전자, 광학 등의 여러 분야에서의 산업적 응용이 크게 기대되는 자료이다. 특히 탄화물형성원소에 대해 안정하여 철계금속의 가공을 위한 공구재료로의 응용 또한 기대되는 재료이다. 특히 탄화물형성원소에 대해 안정하여 철계금속의 가공을 위한 공구재료로의 응용 또한 크게 기대된다. 이 때문에 각종의 PVD, CVD 공정을 이용하여 c-BN 박막의 합성에 대한 연구가 광범위하게 진행되어 많은 성공사례들이 보고되고 있다. 그러나 이러한 c-BN 박막의 유용성에도 불구하고 아직 실제적인 응용이 이루어지지 못한 것은 증착직후 급격한 박리현상을 보이는 c-BN 박막의 밀착력문제때문이다. 본 연구에서는 평행자기장을 부가한 ME-ARE(Magnetically Enhanced Activated Reactive Evaporation)법을 이용하여 c-BN 박막을 합성하고, 합성된 c-BN 박막의 밀착력에 미치는 공정인자의 영향을 규명하여, 급격한 박리현상을 보이는 c-BN 박막의 밀착력 향상을 위한 최적 공정을 도출하고자 하였다. BN 박막 합성은 전자총에 의해 증발된 보론과 (질소+아르곤) 플라즈마의 활성화반응증착(activated reactive evaporation)에 의해 이루어졌다. 기존의 ARE장치와 달리 열음극(hot cathode)과 양극(anode)사이에 평행자기장을 부여하여 플라즈마를 증대시켜 반응효율을 높혔다. 합성실험용 모재로는 p-type으로 도핑된 (100) Si웨이퍼를 30$\times$40 mm크기로 절단 후, 100%로 희석된 완충불산용액에 10분간 침적하여 표면의 산화층을 제거한후 사용하였다. c-BN 박막을 얻기 위한 주요공정변수는 기판바이어스 전압, discharge 전류, Ar/N가스유량비이었다. 증착공정 인자들을 변화시켜 다양한 조건에서 c-BN 박막의 합성하여 밀착력 변화를 조사하였다. 합성된 박막의 결정성 분석을 FTIR을 이용하였으며, Bn 박막의 상 및 미세구조관찰을 위해 투과전자현미경(TEM;Philips EM400T) 분석을 병행하였고, 박막의 기계적 물성 평가를 위해 미소경도를 측정하였다. 증착된 c-BN 박막은 3~10 GPa의 큰 잔류응력으로 인해 증착직후 급격한 박리현상을 보였다. 이의 개선을 위해 증착중 기판바이어스 제어 및 후열처리를 통해 밀착력을 수~수백배 향상시킬 수 있었다. c-BN 박막의 합성을 위해서는 증착중인 박막표면으로 큰 에너지를 갖는 이온의 충돌이 필요하기 때문에 기판 바이어스가 요구되는데, c-BN의 합성단계를 핵생성 단계와 성장 단계로 구분하여 인가한 기판바이어스를 달리하였다. 이 결과 그림 1에서 나타낸 것처럼 c-BN 박막의 핵생성에 필요한 기판바이어스의 50% 정도만을 인가하였을 때 잔류응력은 크게 경감되었으며, 밀착력이 크게 향상되었다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.27 no.6
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• pp.275-281
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• 2017

AlN is a promising material for wide band gap and high-frequency electronics device due to its wide bandgap and high thermal conductivity. AlN has advantages as materials for power semiconductors with a larger breakdown field, and a smaller specific on-resistance at high voltage. The growth of a p-type AlN epilayer with high conductivity is important for a manufacturing an AlN-based applications. In this paper, Mg doped AlN epilayers were grown by a mixed-source HVPE. Al and Mg mixture were used as source materials for the growth of Mg-doped AlN epilayers. Mg concentration in the AlN was controlled by modulating the quantity of Mg source in the mixed-source. Surface morphology and crystalline structure of AlN epilayers with different Mg concentrations were characterized by FE-SEM and HR-XRD. XPS spectra of the Mg-doped AlN epilayers demonstrated that Mg was doped successfully into the AlN epilayer by the mixed-source HVPE.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.