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http://dx.doi.org/10.5573/ieek.2013.50.7.087

A 2.5 Gb/s Burst-Mode Clock and Data Recovery with Digital Frequency Calibration and Jitter Rejection Scheme  

Jung, Jae-Hun (School of Electrical and Electronics Engineering, Chung-Ang University)
Jung, Yun-Hwan (School of Electrical and Electronics Engineering, Chung-Ang University)
Shin, Dong Ho (School of Electrical and Electronics Engineering, Chung-Ang University)
Kim, Yong Sin (School of Electrical and Electronics Engineering, Chung-Ang University)
Baek, Kwang-Hyun (School of Electrical and Electronics Engineering, Chung-Ang University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.7, 2013 , pp. 87-95 More about this Journal
Abstract
In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.
Keywords
Clock and Data Recovery(CDR); burst-mode; frequency calibration; jitter rejection; Passive Optical Network(PON);
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
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