1 |
B. R. Jackson, C. E. Saavedra, 'An L-band CMOS frequency doubler using a time-delay technique', Silicon Monolithic Integrated Circuits in RF Systems, Jan. 2006
|
2 |
Z. Wang, 'CMOS adjustable Schmitt triggers', IEEE Transactions on Instrumentation and Measurement, vol. 40, no. 3, Jun. 1991
|
3 |
M. Styeyaert, W. Sansen, 'Novel CMOS Schmitt trigger', Electronics Letters, vol. 22, no. 4, pp. 203- 204, Feb. 1986
DOI
ScienceOn
|
4 |
S. J. Seo, Y. C. Jeong, J. S. Lim, B. Gray, and J. S. Kenney, 'A novel design of frequency tripler using composite right/left handed transmission line', IEEE IMS Proceedigns, pp. 2185-2188, Jun. 2007
|
5 |
S. K. Park, N. S. Ryu, H. J. Choi, Y. C. Jeong, and C. D. Kim, 'A novel design of frequency multiplier using feedforward technique and defected ground structure', 36th European Microwave Conference Proceedings, pp. 224-227, Sep. 2006
|
6 |
F. Cheng, C. Chen, and O. Choy, 'A 1.0 um CMOS all digital clock multiplier', Proc. IEEE 40th Midwest Symposium on Circuits and Systems, vol. 1, pp. 460-462, Aug. 1997
|
7 |
I. A. Young, J. K. Greason, and K. L. Wong, 'A PLL clock generator with 5 to 110 MHz of lock range for microprocessors', IEEE Journal of Solid-State Circuits, vol. 27, no. 11, Nov. 1992
|
8 |
Y. Lee, S. Choi, S. Kim, J. Lee, and K. Kim, 'Clock multiplier using digital CMOS standard cells for high-speed digital communication systems', Elect ronics Letters, vol. 35, no. 24, pp. 2073-2074, Nov. 1999
DOI
ScienceOn
|
9 |
F. Ellinger, 'Ultracompact SOI CMOS frequency doubler for low power applications at 26.5-28.5 GHz', IEEE Microwave and Wireless Components Letters, vol. 14, no. 2, Feb. 2004
DOI
ScienceOn
|
10 |
A. Pfister, 'Novel CMOS schmitt trigger with controllable hysteresis', Electronics Letters, vol. 28, no. 7, pp. 639-641, Mar. 1992
DOI
ScienceOn
|