• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.693-695
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• 2012

This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET as the device to be able to use until nano scale has the adventage to reduce the short channel effects. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change od the breakdown voltage for gate oxide thickness and channel thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.372-377
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• 2013

This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET has the advantage to reduce the short channel effects as improving the current controllability of gate. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change of the breakdown voltage for gate oxide thickness and channel thickness.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.748-751
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• 2014

This paper has analyzed threshold voltage movement for channel doping concentration of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is generally fabricated with low doping channel and fully depleted under operation. Since impurity scattering is lessened, asymmetric DGMOSFET has the adventage that high speed operation is possible. The threshold voltage movement, one of short channel effects necessarily occurred in fine devices, is investigated for the change of channel doping concentration in asymmetric DGMOSFET. The analytical potential distribution of series form is derived from Possion's equation to obtain threshold voltage. The movement of threshold voltage is investigated for channel doping concentration with parameters of channel length, channel thickness, oxide thickness, and doping profiles. As a result, threshold voltage increases with increase of doping concentration, and that decreases with decrease of channel length. Threshold voltage increases with decrease of channel thickness and bottom gate voltage. Lastly threshold voltage increases with decrease of oxide thickness.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.179-183
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• 2012

The random dopant fluctuation (RDF) effects of tunneling field-effect transistors (TFETs) have been observed by using atomistic 3-D device simulation. Due to extremely low body doping concentration, the RDF effects of TFETs have not been seriously investigated. However, in this paper, it has been found that the randomly generated and distributed source dopants increase the variation of threshold voltage ($V_{th}$), drain induced current enhancement (DICE) and subthreshold slope (SS) of TFETs. Also, some ways of relieving the RDF effects of TFETs have been presented.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.258-258
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• 2010

레이저 유기 형광법은 비침투적인 방법으로 플라즈마를 진단할 수 있는 장점이 있다. 특히 헬륨 플라즈마 내에서 전기장이 존재하는 경우에 헬륨의 에너지 준위가 분리되는 STARK 효과를 이용하여 기판 부근에 발생한 쉬스 내의 전기장을 측정할 수 있다[1]. 그러나 플라즈마의 생성을 위한 RF 소스와 레이저 간의 위상이 동기화 되지 않는 경우엔, 그 결과 값의 보정이 필요하다. 외부의 전기장이 시변하는 경우에 각각의 위상에서 헬륨의 여기종이 느끼는 전기장의 세기는 다르다. 따라서 레이저가 어떤 타이밍에 입사되는 가에 따라 신호의 분리되는 정도가 달라지는데, 레이저와 외부 전기장의 위상을 동기화하지 않은 경우에는 관측된 신호는 각각의 위상에서 여러 가지로 분리된 신호가 더해진 합의 형태로 나타난다. 이는 외부에서 인가된 전기장의 가장 큰 값을 나타낸다고 알려져 있었다[2]. 그러나 레이저 유도 형광 신호는 넓게 분산을 가지므로 이는 보정되어야 한다. 본 연구에서는 각각의 위상에서 출력되는 형광 신호를 구하고 시간의 영역에서 1주기 동안 적분하여 실제로 관측될 레이저 유도 형광신호의 보정치를 계산하였다. 이를 실험적으로 검증하기 위해서 유도 결합 플라즈마 반응 챔버 내에서 플라즈마를 방전시킨 후에, 레이저 유도 형광법을 사용하여 기판 위에 생성된 쉬스 내의 전기장을 측정하였다. 그리고, 랑뮤어 프루브를 이용하여 벌크 플라즈마 내의 플라즈마 전압을 구하고, 이를 적분 상수로 삼아 쉬스 내의 전위 분포를 구하였다. 또한 기판에 인가되는 전압을 직접 측정하여 위에서 구한 전위 분포치와 보정을 한 후의 전위 분포치를 비교, 검토하여 보정치를 검증하였다.

• Journal of IKEEE
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• v.6 no.2 s.11
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• pp.136-145
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• 2002

The simulator for the analysis of the lattice temperature under the steady-state condition is developed. The heat flow equation using the Slotboom variables is discretized and the integration method of the thermal conductivity without using the numerical analysis method is presented. The simulations are executed on the $N^+P$ junction diode and BJT to verify the proposed method. The average relative error of the lattice temperature of $N^+P$ diode compared with DAVINCI is 2% when 1.4[V] forward bias is applied and the average relative error of the lattice temperature of BJT compared with MEDICI is 3% when 5.0[V] is applied to the collector contact and 0.5[V] is applied to the base contact. BANDIS using the proposed method of integration of thermal conductivity needs 3.45 times of matrix solution to solve one bias step and DAVINCI needs 5.1 times of matrix solution MEDICI needs 4.3 times of matrix solution.

• Journal of IKEEE
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• v.21 no.1
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• pp.96-99
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• 2017

In this study the influence of the random dopant fluctuation (RDF) depending on the halo and LDD implantations for the metal-oxide-semiconductor field effect transistor is investigated through the 3D atomistic device simulation. For accuracy in calculation, the kinetic monte carlo method that models individual impurity atoms and defects in the device was applied to the atomistic simulation. It is found that halo implantation has the greater influence on RDF effects than LDD implantation; three-standard deviation of $V_{TH}$ and $I_{ON}$ induced by halo implantation is about 6.45 times and 2.46 times those of LDD implantation. The distributions of $V_{TH}$ and $I_{ON}$ are also displayed in the histograms with normal distribution curves.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1069-1074
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• 2017

Reduction of breakdown voltage is serious short channel effect (SCE) by shrink of channel length. The deviation of breakdown voltage for doping concentration is investigated with structural parameters of sub-10 nm double gate (DG) MOSFET in this paper. To analyze this, thermionic and tunneling current are derived from analytical potential distribution, and breakdown voltage is defined as drain voltage when the sum of two currents is $10{\mu}A$. As a result, breakdown voltage increases with increase of doping concentration. Breakdown voltage decreases by reduction of channel length. In order to solve this problem, it is found that silicon and oxide thicknesses should be kept very small. In particular, as contributions of tunneling current increases, breakdown voltage increases.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1771-1777
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• 2016

In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.688-690
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• 2017

Reduction of breakdown voltage is serious short channel effect (SCE) by shrink of channel length. The SCE occurred in on-state transistor raises limitation of operation range of transistor. The deviation of breakdown voltage for doping concentration is investigated with structural parameters of sub-10 nm double gate (DG) MOSFET in this paper. To analyze this, thermionic and tunneling current are derived from analytical potential distribution, and breakdown voltage is defined as drain voltage when the sum of two currents is $10{\mu}A$. As a result, breakdown voltage increases with increase of doping concentration. Breakdown voltage decreases by reduction of channel length. In order to solve this problem, it is found that silicon and oxide thicknesses should be kept very small. In particular, as contributions of tunneling current increases, breakdown voltage increases.