• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.657-662
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• 2014

This paper has analyzed the subthreshold swings for top and bottom gate voltages of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates. The subthreshold swing, therefore, has to be analyze not only for top gate voltage, but also for bottom gate voltage. In the pursuit of this purpose, Poisson equation has been solved to obtain the analytical solution of potential distribution with Gaussian function, and the subthreshold swing model has been presented. As a result to observe the subthreshold swings for the change of top and bottom gate voltage using this subthreshold swing model, we know the subthreshold swings are greatly changed for gate voltages. Especially we know the conduction path has been changed for top and bottom gate voltage and this is expected to greatly influence on subthreshold swings.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.704-707
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• 2013

This paper has analyzed the subthreshold swings for top and bottom gate voltages of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates. The subthreshold swing, therefore, has to be analyze not only for top gate voltage, but also for bottom gate voltage. In the pursuit of this purpose, Poisson equation has been solved to obtain the analytical solution of potential distribution with Gaussian function, and the subthreshold swing model has been presented. As a result to observe the subthreshold swings for the change of top and bottom gate voltage using this subthreshold swing model, we know the subthreshold swings are greatly changed for gate voltages. Especially we know the conduction path has been changed for top and bottom gate voltage and this is expected to greatly influence on subthreshold swings.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.4
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• pp.56-61
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• 2009

This paper presents the ground surface potential profiles and hazard voltages around the metallic structure connected to a small-sized model ground electrode. Because it is very difficult to draw valid conclusions concerning a general grounding problem from actual field data, scale model tests can be used to determine the touch and stop voltages and surface potential profiles around ground electrode. In this work, a hemispherical vessel with a diameter of 1,100[mm] was employed to simulate uniform soil. As a result, the ground surface potential around the ground electrode was significantly raised In particular the ground surface potential at the just upper point of ground rod was higher than other points. When the buried depth of ground rod is increased, the ground surface potential and step voltage were lowered but the touch voltage was elevated.

• Electrical & Electronic Materials
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• v.5 no.3
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• pp.320-327
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• 1992

Twin-tub CMOS 공정에 의해 제작된 서브마이크로미터 채널길이를 갖는 n채널 및 p채널 MOSFET의 특성을 고찰하였다. n채널 및 p채널 영역에서의 불순물 프로파일과 채널 이온주입 조건에 따른 문턱전압의 의존성 및 퍼텐셜 분포를 SUPREM-II와 MINIMOS 4.0을 사용하여 시뮬레이션하였다. 문턱전압 조정을 위한 counter-doped 보론 이온주입에 의해 p채널 MOSFET는 표면에서 대략 0.15.mu.m의 깊이에서 매몰채널이 형성되었다. 각 소자의 측정 결과, 3.3[V] 구동을 위한 충분한 여유를 갖는 양호한 드레인 포화 특성과 0.2[V]이하의 문턱전압 shift를 갖는 최소화된 짧은 채널 효과, 10[V]이상의 높은 펀치쓰루 전압과 브레이크다운 전압, 낮은 subthreshold 값을 얻었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.1-7
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• 2009

In this paper, a simple analytical model for deriving the threshold voltage of a short-channel intrinsic-body SDG SOI MOSFET is suggested. Using the iteration method, both Laplace equations in intrinsic silicon body and gate oxide are solved two-dimensionally. Obtained potential distributions in both regions are expressed in terms of fourth and fifth-order of the coordinate perpendicular to the silicon channel direction. Making use of them, the surface potential is obtained to derive the threshold voltage in a closed-form. Simulation results show the fairly accurate dependencies of the threshold voltage on the various device parameters and applied bias voltages.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.9-16
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• 2008

In this paper, a simple analytical model for deriving the threshold voltage of a short-gate SOI MESFET is suggested. Using the iteration method, the Poisson equation in the fully depleted silicon channel and the Laplace equation in the buried oxide region are solved two-dimensionally, Obtained potential distributions in each region are expressed in terms of fifth-order of $\chi$, where $\chi$ denotes the coordinate perpendicular to the silicon channel direction. From them, the bottom channel potential is used to describe the threshold voltage in a closed-form. Simulation results show the dependencies of the threshold voltage on the various device geometry parameters and applied bias voltages.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.789-794
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• 2017

Subthreshold current model is presented using analytical potential distribution of junctionless cylindrical surrounding-gate (CSG) MOSFET and threshold voltage shift is analyzed by this model. Junctionless CSG MOSFET is significantly outstanding for controllability of gate to carrier flow due to channel surrounded by gate. Poisson's equation is solved using parabolic potential distribution, and subthreshold current model is suggested by center potential distribution derived. Threshold voltage is defined as gate voltage corresponding to subthreshold current of $0.1{\mu}A$, and compared with result of two dimensional simulation. Since results between this model and 2D simulation are good agreement, threshold voltage shift is investigated for channel dimension and doping concentration of junctionless CSG MOSFET. As a result, threshold voltage shift increases for large channel radius and oxide thickness. It is resultingly shown that threshold voltage increases for the large difference of doping concentrations between source/drain and channel.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.6
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• pp.83-88
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• 2010

In this paper, to propose a valid method solving a problem relevant to grounding from actual field data, the experimental results relevant to touch and step voltages and surface potential profiles measured around the real-sized and small-sized grounding electrode models were described. The ground surface potential profiles and dangerous voltages around the concrete pedestals employed in street facilities such as street lamps, traffic signal lamp and controllers as a case study were measured and discussed. The hemispherical cell with a diameter of 1,160[mm] was employed to simulate uniform soil. As a result, the results measured with the small-sized model were in reasonably agreement with the data obtained from the real-sized installation. It was found that the small-sized model test could be employed as a useful means evaluating the dangerous voltages around grounding electrodes installed at the inaccessible areas such as mountains, underground, underwater, and so on.

• Polymer(Korea)
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• v.28 no.5
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• pp.361-366
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• 2004

The poling characteristics of PVDF (poly(vinylidene fluoride)) film was investigated by measuring the electric voltage generated by the external load for the distributed tactile sensor applications. The poling conditions for the PVDF films were controlled by changing temperature and electric field, and the resulting crystal structure of the $\beta$-phase crystal was confirmed by FT-IR, DSC, and XRD experiments. The $\beta$-phase crystal was increased with the poling temperature and poling voltage, and subsequently the permittivity of the Poled PVDF films was increased. Finally, the prototype tactile sensor was tested by a 8 $\times$ 8 may circuit exhibiting high voltage signal for the highly poled PVDF films.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.2000-2006
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• 2011

In this paper, the drain induced barrier lowering(DIBL) for doping distribution in the channel has been analyzed for double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studing because of adventages to be able to reduce the short channel effects(SCEs) to occur in convensional MOSFET. DIBL is SCE known as reduction of threshold voltage due to variation of energy band by high drain voltage. This DIBL has been analyzed for structural parameter and variation of channel doping profile for DGMOSFET. For this object, The analytical model of Poisson equation has been derived from Gaussian doping distribution for DGMOSFET. To verify potential and DIBL models based on this analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and DIBL for DGMOSFET has been investigated using this models.