• Journal of the Korean Crystal Growth and Crystal Technology
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• v.8 no.4
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• pp.581-586
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• 1998

We investigated the effect of mechanical back side damage in Czochralski grown silicon wafer. The intensity of mechanical damage was evaluated by minority carrier recombination lifetime by laser excitation/microwave reflection photoconductivity decay method, degree of X-ray diffuse scattering, X-ray section topography, and wet oxidation/preferential etching methods. The data indicate that the higher the mechanical damage intensity, the lower the minority carrier lifetime, and the magnitude of diffuse scattering and X-ray excess intensity increased proportionally, and it was at Grade 1:Grade 2:Grade 3=1:7:18.4 that the normalized relative quantization ratio of excess intensity in damaged wafer was calculated, which are normalized to the excess intensity from sample Grade 1.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.1
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• pp.61-65
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• 2010

A commercially available soft PZT wafer that is poled in thickness direction is subjected to longitudinal tensile stress loading in both short and open-circuit conditions. Variations of electric displacement in thickness direction and in-plane strains are measured over time during the loading. Different material responses in the two electrical boundary conditions are explained by the effects of piezoelectrically produced internal electric field on linear material moduli and domain switching mechanisms. Finally, a free energy model of normal distribution is introduced to explain the observed creep behavior, and its predictions are compared with experimental observations.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.8
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• pp.808-820
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• 2014

In this paper, we fabricated two on-wafer type DUT(Device-Under-Test)s; a 10-dB attenuator and an amplifier using commercially available MMIC and we proposed the measurement method of the noise parameters for the two fabricated DUTs. Since the 10-dB attenuator DUT is a passive device, its noise parameters can be accurately determined when its S-parameters are measured. In the case of the amplifier DUT, its noise parameters are available in the datasheet. Hence, the measured noise parameters using the proposed method can be assessed by comparing with the known noise parameters. The noise parameter measurement method having been presented by the authors requires the S-parameters of the 8-port network used in the measurement and limited to coaxial type DUTs. When on-wafer probes are included in the 8-port network, the 8-port S-parameters requires the measurements with different kinds of connectors. In this paper, we obtained the 8-port S-parameters using the Smart-Cal function in the network analyzer. The measured noise parameters shows about ${\pm}0.2dB$ fluctuations for $NF_{min}$. Other noise parameters with the frequency change show good agreement with the expected results.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.474-474
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• 2010

현재 반도체시장의 확장으로 인해서 기존의 300mm 웨이퍼에서 450mm의 웨이퍼를 사용하는 공정으로 변화하는 추세이다. 450mm 웨이퍼로 대면적 화되면서 기존 300mm 공정 때보다 훨씬 효율적인 플라즈마 소스 즉, 고밀도이고, 고균등화(high uniformity) 플라즈마 소스를 필요로 한다. 본 논문에서는 고밀도 플라즈마 소스인 유도 결합형 플라즈마(Inductively Coupled Plasma ; ICP)에 축 방향의 약한 자기장을 인가시킨 자화된 유도결합형 플라즈마(Magnetized Inductively Coupled Plasma : MICP)[1]를 제안하여 기존 ICP와의 차이점을 살펴보았다. 실험 방법으로 레이저 유기 형광법(Laser Induced Fluorescence : LIF)[2]을 이용하여 플라즈마 쉬스(Sheath) 내의 전기장을 외부 자기장의 변화에 따라 높이별로 측정하고 그 결과로부터 쉬스의 전기적 특성을 살펴보았다. 플라즈마의 특성상 탐침이나 전극에 전압을 인가하면 그 주위로 디바이 차폐(Debye Shielding)현상이 일어나서 플라즈마 왜곡이 일어난다. 그렇기에 플라즈마, 특히 플라즈마 쉬스의 특성을 파악하기 위해서 레이저라는 기술을 사용하였다. 레이저는 고가의 장비이고 그 사용에 많은 경험지식(know-how)를 필요로 하지만 플라즈마를 왜곡시키지 않고, 플라즈마의 밀도, 온도, 전기장 등 많은 상수(parameter)들을 얻어 낼 수 있다. 또한 3차원적으로 높은 분해능을 가지고 있는 장점이 있다. 강한 전기장이 있는 곳에서 입자들의 고에너지 준위가 전기장의 세기에 비례하여 분리되는 Stark effect[3] 이론을 이용하여 플라즈마 쉬스내의 전기장을 측정하였다. 실험은 헬륨가스 700mTorr 압력에서 이루어졌다. 기판의 파워를 50W에서 300W까지 변화시키면서 기판에 생기는 쉬스의 전기장의 변화를 살펴보았고, 자기장을 인가한 후 동일한 실험을 하여 자기장의 유무에 따른 플라즈마 쉬스의 전기장 변화를 살펴보았다. 실험결과 플라즈마 쉬스의 전기장의 변화는 기판의 파워와 플라즈마 밀도에 크게 의존함을 알았다. 기판의 파워가 커질수록 쉬스의 전기장은 커지고, 기판에 생기는 Self Bias Voltage역시 음의 방향으로 커짐을 확인 하였다. 또한 자기장을 걸어주었을 경우 쉬스의 두께가 얇아짐으로써 플라즈마의 밀도가 증가했음을 확인 할 수 있었다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.807-808
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.657-658
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.06a
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• pp.755-756
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• 2007

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Korean Chemical Engineering Research
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• v.46 no.2
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• pp.389-396
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• 2008

The effect of thermal cycling on bond strength and residual stress at the interface between benzocyclobutene (BCB) and plasma enhanced chemical vapor deposited (PECVD) silicon dioxide ($SiO_2$) coated silicon wafers were evaluated by four point bending and wafer curvature techniques. Wafers were bonded using a pre-established baseline process. Thermal cycling was done between room temperature and a maximum peak temperature. In thermal cycling performed with 350 and $400^{\circ}C$ peak temperature, the bond strength increased substantially during the first thermal cycle. The increase in bond strength is attributed to the relaxation in residual stress by the condensation reaction of the PECVD $SiO_2$: this relaxation leads to increases in deformation energy due to residual stress and bond strength.

• Journal of IKEEE
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• v.22 no.2
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• pp.427-431
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• 2018

This research was worked about $Ga_2O_3$ Epi wafer that was one of the mose wide band gap semiconductors to be used power semiconductor industry. This wafer was grown $5.3{\mu}m$ thickness on Sn doped $Ga_2O_3$ Substrate by HVPE(Hydride Vapor Phase Epitaxy). Generally, we can fabricate 600V class power semiconductor devices when the thickness of compoound power semiconductor is $5{\mu}m$. but in case of $Ga_2O_3$ Epi wafer, we can obtain over 1000V class. As a result of J-V measurment of the grown $Ga_2O_3$ Epi wafer, we obtain $2.9-7.7m{\Omega}{\cdot}cm^2$ on resistance. Specially, in case of reverse, we comfirmed a little leakage current when the reverse voltage is over 200V.