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http://dx.doi.org/10.6117/kmeps.2012.19.3.037

Ti/Cu CMP process for wafer level 3D integration  

Kim, Eunsol (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
Lee, Minjae (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
Kim, Sungdong (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
Kim, Sarah Eunkyung (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology)
Publication Information
Journal of the Microelectronics and Packaging Society / v.19, no.3, 2012 , pp. 37-41 More about this Journal
Abstract
The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.
Keywords
Cu CMP; Dishing; Erosion; Wafer Level Integration;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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