• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.13-20
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• 2008

This paper describes the methods of spacer-fabrication for wafer-level CIS(CMOS Image Sensor) assembly. We propose three methods using SU-8, PDMS and Si-interposer for the spacer-fabrication. For SU-8 spacer, novel wafer rotating system is developed and for PDMS(poly-dimethyl siloxane) spacer, new fabrication-method is used to bond with alignment of glass/PDMS/glass structure. And for Si-interposer, DFR(Dry Film Resist) is used as adhesive layer. The spacer using Si-interposer has the strongest bonding strength and the strength is 32.3MPa with shear.

• The Journal of Korea Robotics Society
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• v.2 no.3
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• pp.249-254
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• 2007

본 논문에서는 웨이퍼 레벨 밀봉 실장된 수직 운동 가속도 신호를 감지할 수 있는 초소형 Z축 가속도 센싱 엘리먼트를 제작하였다. 초소형 Z축 가속도 센싱 엘리먼트는 수직 방향의 정전용량 변화를 필요로 하기 때문에 단일 기판상에 수직 단차의 형성을 가능케 하는 확장된 희생 몸체 미세 가공 기술 (Extended Sacrificial Bulk Micromachining, ESBM) 을 이용하여 제작되었다. 확장된 희생 몸체 미세 가공 기술을 이용하면 정렬오차가 없이 상하부 양쪽에 수직 단차를 갖는 실리콘 구조물의 제작이 가능하다. 또한, MEMS 센싱 엘리먼트의 부유된 실리콘 구조물을 보호하기 위하여 웨이퍼 레벨 밀봉 실장 기술이 적용하여 고신뢰성, 고수율, 고성능의 Z축 가속도 센서를 제작하였다. 신호 처리 회로와 가속도 센서를 결합하여 Z축 가속도 센싱 시스템을 제작하였고 운동가속도 범위 10 g 이상, 정지 드리프트 17.3 mg 그리고 대역폭 60 Hz 이상의 성능을 나타내었다.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2553-2556
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• 2003

In the semiconductor equipment industry, the SECS/GEM protocol has been recognized as the communication standard, but in our 300mm wafer aligner being developed, this capability has not been equipped yet. In this study, we present the realization of SECS-I, SECS-II and HSMS communication protocol between factory host computer and wafer aligner. Its validity is shown in actual test environment.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1993.10a
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• pp.243-248
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• 1993

New methodology for fiducial alignment is proposed to improve the alignment accuracy in wafer steppers. The positioning error is detected by PSD(Position Sensitive Detector)when 2-dimensional vernier patterns on a reticle on a reticle are projected on the fiducial marks of wafer stage. The width and period of vernier patterns are deter mined to get the highest S/N ratio for the exposure wavelength 248.4nm of KrF excimer laser. This new method has an advantage of higher accuracy and faster alignment over the conventional one.

• Proceedings of the Optical Society of Korea Conference
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• 1995.06a
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• pp.68-74
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• 1995

한국전자통신연구소에서 개발된 바 있는 KrF 엑시머 레이저 스탭퍼의 개발 과정과 그 결과를 보이고, 동시에 현재 개발중인 ArF 엑시머 레이저 스텝퍼의 진행상황을 보고한다. 본 논문에서는 스탭퍼의 주요 구성요소인 조명계, 투영광학계, 웨이퍼 자동초점 및 자동정렬 시스템을 중심으로 설명하여, KrF와 ArF 에시머 레이저 스탭퍼간의 차이점과 그 특성들을 상호 비교한다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2004.05a
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• pp.268-271
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• 2004

반도체 가공공정에서 웨이퍼의 정렬이나 각종 초정밀 가공에서 가공물의 각도를 미체 조정하기 위한 초정밀 메커니즘을 제안하였다. 일반적으로 각도를 결정하는 메커니즘은 기어를 이용한다. 기어를 이용할 경우 회전 분해능을 높일 수 있으나 기어의 백래쉬에 의한 오차가 있어 보다 높은 정밀도를 구현하기가 어렵다. 본 논문에서는 직접구동(direct drive) 방식과 이중서보(dual servo) 방식을 이용하여 기어를 사용하지 않고 회전 스테이지를 구현하였다.

• Journal of IKEEE
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• v.23 no.2
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• pp.594-598
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• 2019

We demonstrate an alternative alignment process using transferring process on solution driven HfZnO film. Parallel pattern is firstly fabricated on a silicon wafer by laser interference lithography. Prepared HfZnO solution fabricated by sol-gel process is spin-coated on a glass substrate. The silicon wafer with parallel pattern is placed on the HfZnO film and annealed at $100^{\circ}C$ for 30 min. After transferring process, parallel grooves on the HfZnO film is obtained which is confirmed by atomic force microscopy and scanning electron microscopy. Uniform liquid crystal alignment is achieved which is attributed to an anisotropic characteristic of HfZnO film by parallel grooves. The liquid crystal cell exhibited a pretilt angle of $0.25^{\circ}$ which showed a homogeneous alignment property.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.11
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• pp.6464-6471
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• 2014

The UV curing method is a popular process for lens molding on a unit wafer. This process, however, has several drawbacks including wafer adhesion during the ejection process after curing, errors in lens shape and wafer warpage due to material shrinkage during the curing process, and lens centering errors on both sides of a wafer. Among these, the lens shape error and warpage are influenced directly by the UV curing process due to factors including the UV radiation uniformity, the degree of cure according to UV intensity, and the shrinkage characteristics of the material. Therefore, a theory is needed not only to understand the change in the material characteristics, such as the shrinkage rate due to the curing reaction, but also to establish a model. In addition, an analysis system is needed to realize the model. This study proposes a new analysis method for the wafer lens molding process by Comsol modeling. This method was verified by comparing the results with those of the actual process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.1
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• pp.461-467
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• 2021

Among the defect factors that can occur when a wafer-level lens is molded using a thermosetting material, the mold sticking problem of a molded lens during the release process can damage the molded substrate and deform the substrate at the wafer level. An experiment was conducted to examine the factors affecting the demolding force in the lens forming process. The demolding force was examined according to the coating material of the molds. The mold was surface-treated with ITO and Ti, followed by plasma treatment in an O2 atmosphere. A DLC coating was then performed, and the curing and releasability were examined. A coating method for the pull-off experiment was selected based on the results. To measure the demolding force according to the curing process conditions, a method of curing at a constant pressure and a method of curing at a constant position were applied. As a result, the TiO2 surface treatment reduced the release force. When cured by controlling the location, curing shrinkage can reduce the adhesion energy of the interface during curing, resulting in better demolding.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.