• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.131-139
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• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.25-32
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• 2009

Recently, research for Network-on-chip(NoC) is progressing. However, due to the increase of system complexity and demand on high performance, conventional copper-based electrical interconnect would be faced with the design limitation of performance, power, and bandwidth. As an alternative to these problems, combined use of Electrical Interconnects(EIs) and Optical Interconnects(OIs) has been introduced. In this paper we propose efficient routing optimization strategy and hybrid switch architecture, which use OIs for critical path and EIs for non-critical path. The proposed method shows up to 25% performance improvement and 38% power reduction.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.7
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• pp.40-48
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• 2015

An optical network-on-chip(ONoC) architecture is emerging as a new paradigm for solving on-chip communication bottleneck. Recent studies on ONoC have been focusing on supporting the parallel transmission and avoiding path collisions using wavelength division multiplexing(WDM). However, since the maximum number of wavelengths, which a single waveguide can accommodate is limited by crosstalk and insertion loss. Therefore previous WDM studies based on incrementing the number of different wavelengths according to the number of nodes would be infeasible due to the implementation complexity. To solve such problems, we combined time division multiplexing(TDM) and wavelength-routed ONoC, along with an optimized channel allocation algorithm, which can minimize the number of extra wavelength channels and latency caused by combining TDM scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.86-94
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• 2007

The NoC (network-on-chip) approach is a promising solution to the increasing complexity of on-chip communication problems because of its high scalability. But, NoC applications generally consume a lot of power, because they require a large design space to accommodate many parallel IPs and network communication channels. It is not easy to analyze the power consumption of NoC applications with conventional simulation methods using simple power models. In addition, there are also many limitations in using sophisticated simulation models because they require long execution time and large efforts. In this paper, we apply a cycle-accurate energy measurement technique and tool to the FPGA prototypes, which are generally used to verify the correctness of SoC designs, as a practical indication of the power consumption of real NoC applications. An NoC-based JPEG encoder implementation is used as a case study to demonstrate the effectiveness of our approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.103-110
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• 2014

Recent TSV based 3D Integrated Circuit (IC) technology needs more powerful thermal management techniques. However, because cooling cost and form factor are restricted, thermal management are emphasis on software based techniques. But in case of throttling thermal management which one of the most candidate technique, increasing bus occupation induce total performance decrease. To solve communication bottleneck issue in TSV based 3D SoC, we proposed adaptive throttling technique Experimental results show that the proposed method can improve throughput by about 72% compare with minimal path routing.

• Information and Communications Magazine
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• v.29 no.11
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• pp.81-93
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• 2012

60GHz 주파수는 최대 9GHz 까지 엄청난 대역폭을 활용하여 Gbps급의 무선전송이 가능한 대역으로서, 최근 이 대역을 댁내 무선전송장치 및 초고속 무선랜에 활용하기 위한 연구가 활발히 진행되고 있다. 이와 같이 60GHz에 대한 관심도가 높아진 이유는, 밀리미터파 통신이 기존에는 무선 백홀용으로 주로 사용되었던것에 비해 지금은 가정 및 사무실내에서의 초고속 네트워크 또는 영상가전에서의 무선 전송장치 등 응용분야의 다변화가 예상됨에 따라, ISM 대역이면서 광대역을 활용할 수 있는 60GHz가 급부상하게 된 것으로 본다. 이와 함께 CMOS 칩기술의 꾸준한 발전으로 현재는 수 십 나노공정을 이용하여 테라헤르쯔 대역에서도 동작하는 칩이 발표되고 있는 바 그동안 60GHz 시장 확산의 가장 큰 걸림돌이 었던 무선 전송장치의 높은 가격, 사이즈, 소모전력의 문제를 한꺼번에 해결할 수 있게 된 점도 이유중 하나이다. 따라서 이와 관련하여 본고에서는 ETRI와 KETI를 중심으로 진행되어 온 "60GHz 무선 전송장치에 탑재 가능한 범용 CMOS 송수신 칩 및 이를 활용한 빔포밍 트랜시버 기술에 관한 연구"를 소개하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.25-32
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• 2011

Networks-on-chip (NoC) is emerging as a key technology to overcome severe bus traffics in ever-increasing complexity of the Multiprocessor systems-on-chip (MPSoC); however traditional electrical interconnection based NoC architecture would be faced with technical limits of bandwidth and power consumptions in the near future. In order to cope with these problems, a hybrid optical NoC architecture which use both electrical interconnects and optical interconnects together, has been widely investigated. In the hybrid optical NoCs, wormhole switching and simple deterministic X-Y routing are used for the electrical interconnections which is responsible for the setup of routing path and optical router to transmit optical data through optical interconnects. Optical NoC uses circuit switching method to send payload data by preset paths and routers. However, conventional hybrid optical NoC has a drawback that concurrent transmissions are not allowed. Therefore, performance improvement is limited. In this paper, we propose a new routing algorithm that uses circuit switching and adaptive algorithm for the electrical interconnections to transmit data using multiple paths simultaneously. We also propose an efficient method to prevent livelock problems. Experimental results show up to 60% throughput improvement compared to a hybrid optical NoC and 65% power reduction compared to an electrical NoC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.7-16
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• 2007

In this paper, we introduce a new design environment for efficient multiprocessor system-on-chip design space exploration. The design environment takes a process network model as input system specification. The process network model has been widely used for modeling signal processing applications because of its excellent modeling power. However, it has limitation in predictability, which could cause severe problem for real time systems. This paper proposes a new approach that enables static analysis of a process network model by converting it to a hierarchical synchronous dataflow model. For efficient design space exploration in the early design step, mapping application to target architectures has been a crucial part for finding better solution. In this paper, we propose an efficient mapping algorithm. Our mapping algorithm supports both single bus architecture and multiple bus architecture. In the experiments, we show that the automatic conversion approach of the process network model for static analysis is performed successfully for several signal processing applications, and show the effectiveness of our mapping algorithm by comparing it with previous approaches.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.