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http://dx.doi.org/10.5573/ieek.2013.50.7.131

A Latency Optimization Mapping Algorithm for Hybrid Optical Network-on-Chip  

Lee, Jae Hun (College of Information & Communication Engineering, Sungkyunkwan University)
Li, Chang Lin (College of Information & Communication Engineering, Sungkyunkwan University)
Han, Tae Hee (College of Information & Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.7, 2013 , pp. 131-139 More about this Journal
Abstract
To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.
Keywords
HONoC; optical interconnect; latency; mapping; path collision;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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