• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.1
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• pp.1-6
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• 2010

본 논문에서는 네트워크 온 칩(NoC: network on chip) 구조에서의 내부 데이터 통신의 성능을 최적화 할 수 있는 새로운 온 칩 네트워크 인터페이스 구조를 제안하였다. 제안하는 NoC 구조는 기본적으로 하드웨어 면적을 줄이기 위하여 XY 라우팅 알고리듬을 기반으로 구현되었으며, 전달되는 패킷의 크기 또는 플릿의 개수를 최소화하기 위하여 Golomb-Rice 인코딩/디코딩 알고리듬에 기반을 둔 하드웨어 압축기/해제기를 이용하여 통신되는 데이터의 양을 크게 줄임으로써 네트워크 지연시간을 최소화 할 수 있는 새로운 구조를 제안하였다. 즉 전송될 데이터는 전송자(sender)의 네트워크 인터페이스에서 내장된 하드웨어 인코더를 통해 압축된 형태로 패킷의 개수를 최소화하여 온 칩 네트워크상의 데이터를 업로드하게 된다. 이러한 압축된 데이터가 리시버(receiver)에 도착하면, 하드웨어 디코더를 통해서 원래의 데이터로 복원된다. 사이클 수준의 시뮬레이터를 통하여 제안된 라우터 구조가 온 칩 시스템의 네트워크 지연시간을 크게 줄일 수 있음을 증명하였다.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.3
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• pp.120-132
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• 2008

Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energy-efficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoC-based systems, including network topology, task assignment, tile mapping, routing path allocation, task scheduling and link speed assignment. Experimental results show that the proposed design technique can reduce energy consumption by 28% on average compared with existing techniques.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.83-93
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• 2014

It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.86-93
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• 2010

A system-on-chip (SoC) includes more functions and requires rapidly increased data bandwidth as the development of semiconductor process technology and SoC design methodology. As a result, the data bandwidth of on-chip-networks in SoCs becomes a key factor of the system performance, and the research on the on-chip-network is performed actively. Either AXI or OCP is considered to a substitute of the AHB which has been the most popular on-chip-network. However, they have much increased number of signal wires, which make it difficult to design the interface logic and the network hardware. The compatibility of the protocols with other protocols is not so good. In this paper, we propose a new interface protocol for on-chip-networks to improve the problems mentioned above. The proposed protocol uses less number of signal wires than that of the AHB and considers the compatibility with other interface protocols such as the AXI. According the analysis results, the performance of the proposed protocol per wire is much better than that of the AXI although the absolute performance is slightly inferior.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.754-766
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• 2010

In the wireless communication protocols, a network device is responsible for the operation of lower-layers. The network device consists of hardware and software modules, so it can be designed using system-on-chip simulator. The simulator design needs the support of a network simulator as well as system-on-chip simulator, because the network device interact with various higher layer communication protocols. Therefore the co-simulator can become a development environment of the network device through the combining of them. In this paper we propose a co-simulator combining these two simulators. The proposed co-simulator does not degrade performance due to integrations. Also, it is easy to integrate them because the implementation of the kernel is independent.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.174-177
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• 2016

Wireless network-on-chip (WNoC) can alleviate critical path problem of existing typical NoCs by integrating radio-frequency module on router. In this paper, core-connection-aware genetic algorithm-based core and WIR mapping methodology at small world WNoC is presented. The methodology could optimize the critical path between cores with heavy communication. The 33% of average latency improvement is achieved compared to random mapping methodology.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.108-116
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• 2013

The input buffer in Network on Chip (NoC) router plays a key role in on-chip-network performance, which is utilized in flow control and virtual channel. However, increase in area and power due to input buffers as the network size gets larger is becoming severe. To solve this problem, a bufferless deflection routing without input buffer was suggested. Since the bufferless deflection routing shows poor performance at high network load, other approaches which combine the deflection routing with small size side buffers were also proposed. Nonetheless these new methods still show deficiencies caused by frequent path collisions. In this paper, we propose a modified deflection routing technique using a location based priority. In comparison with existing deflection routers, experimental results show improvement by 12% in throughput with only 3% increase in area.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.32 no.5
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• pp.34-41
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• 2014

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.410-415
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• 2002

This paper describes the implementation of a SoC(System-on-a-Chip) and an ISDN communication terminal by the SoC in ISDN network. The SoC has been developed with the functions of 32-bit ARM7TDMI RISC core processor, network connection with S/T interface, TDM--bus interface and voice codec, user interface. And we also review the developed software structure and the ISDN service protocol procedures which are working on the SoC. And finally this paper describers a structure of an ISDN terminal equipment using the implemented SoC and terminal software.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.68-75
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• 2016

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.