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Communication Optimization for Energy-Efficient Networks-on-Chips  

Shin, Dong-Kun (성균관대학교 정보통신공학부)
Kim, Ji-Hong (서울대학교 컴퓨터공학부)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.35, no.3, 2008 , pp. 120-132 More about this Journal
Abstract
Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energy-efficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoC-based systems, including network topology, task assignment, tile mapping, routing path allocation, task scheduling and link speed assignment. Experimental results show that the proposed design technique can reduce energy consumption by 28% on average compared with existing techniques.
Keywords
network-on-chip; low-power; design automation;
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1 C. Marcon, N. Calazans, F. Moraes, A. Susin, I. Reis, and F. Hessel. Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. In Proc. Design, Automation and Test in Europe Conference, pages 502-507, 2005
2 T. Lei and S. Kumar. A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture. In Proc. Euromicro Symposium on Digital Systems Design, pages 180-187, 2003
3 T. Simunic and S. Boyd. Managing Power Consumption in Networks on Chips. In Proc. Design, Automation, and Test In Europe, pages 110-116, 2002
4 X. Chen and L.-S. Peh. Leakage Power Modeling and Optimization in Interconnection Networks. In Proc. International Symposium on Low Power Electronics and Design, pages 90-95, 2003
5 H.-S. Wang, L.-S. Peh, and S. Malik. Power-Driven Design of Router Microarchitectures in On-Chip Networks. In Proc.International Symposium on Microarchitecture, pages 105-116, 2003
6 L. Shang, L.-S. Peh, and N. K. Jha. Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In Proc. International Symposium on High-Performance Computer Architecture, 2003
7 J. Kim and M. Horowitz. Adaptive Supply Serial Links with Sub-1V Operation and Per-pin Clock Recovery. In Proc. International Solid-State Circuits Conference, 2002
8 D. Shin and J. Kim. Power-Aware Communication Optimization for Networks-on-Chips with Voltage Scalable Links. In Proc. International Conference on Hardware/Software Codesign and System Synthesis, pages 170-175, 2004
9 H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik. Orion: A Power-Performance Simulator for Interconnection Networks. In Proc. International Symposium on Microarchitecture, pages 294-305, 2002
10 W. J. Dally and B. Towles. Route Packets, Not Wires: On-chip Interconnection Networks. In Proc. Design Automation Conference, pages 684-689, 2001
11 Umit Y. Ogras and R. Marculescu. Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach. In Proc. Design, Automation and Test in Europe Conference, pages 352-357, 2005
12 A. B. Kahng and B. R. Moon. Toward More Powerful Recombinations. In Proc. International Conference on Genetic Algorithms, pages 96-103, 1995
13 J. Hu and R. Marculescu. Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures. In Proc. Design, Automation and Test in Europe Conference, pages 10688-10693, 2003
14 L. Benini and G. De Micheli. Networks on Chip: A New SoC Paradigm. IEEE Computer, 35(1): 70-78, 2002
15 J. Duato, S. Yalamanchili, and L. Ni. Interconnection Networks. Morgan Kaufmann, 1997
16 I. Oliver, D. Smith, and J. Holland. A Study of Permutation Crossover Operations on the Traveling Salesman Problem. In Proc. International Conference on Genetic Algorithm, pages 224-230, 1987
17 N. Eisley and L.-S. Peh. High-Level Power Analysis for On-Chip Networks. In Proc. Design, Automation and Test in Europe Conference, pages 10688-10693, 2003
18 A. Jalabert, S. Murali, L. Benini, and G. De Micheli. xPipesComiler: A Tool for Instantiating Application-Specicific NoCs. In Proc. Design, Automation, and Test in Europe, pages 20884-20889, 2004
19 V. Soteriou and L.-S. Peh. Dynamic Power Management for Power Optimization of Interconnection Networks Using On/Off Links. In Proc. Symposium on High Performance Interconnects, pages 15-20, 2003
20 F. Worm, P. Ienne, P. Thiran, and G. De Micheli. An Adaptive Low Power Transmission Scheme for On-chip Networks. In Proc. International System Synthesis Symposium, pages 92-100, 2002
21 M. T. Schmitz and B. M. Al-Hashimi. Considering Power Variations of DVS Processing Elements for Energy Minimisation in Distributed Systems. In Proc. International Symposium on System Synthesis, pages 250-255, 2001