• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.522-525
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• 1998

본 논문에서는 아날로그 증폭기의 특성 개선을 통해 아날로그 신호처리 시스템의 동작속도를 향상시키기 위해서 2단 연산증폭기 (two-stage opamp:TSO)의 주파수 응답 특성과 이득을 개선하기 위한 회로를 설계하고 시물레이션을 통해서 설계된 회로의 우수성을 증명하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Korean Institute of Telematics and Electronics
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• v.9 no.5
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• pp.6-11
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• 1972

A general active RC network synthesis procedure which realizes any stable transfer function is described. The network elements are only R's, C's and OA's, and the network configuration are well suited for construction using thin-film RC networks and integrated cil'suit operational amplifiers. Poles and transmission zeros can be adjusted independently to each other and are qu;te insensitive to element variations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.100-105
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• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.1
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• pp.25-29
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• 1984

The active compensation of operational amplifeir is that it compensates the phase shift and the attennation of gain of OP Amp, according as the frequency increases. The compensation circuit is applied to VCVS and interting integrator. For VCVS, the phase shift of proposed compensated circuit is not concern with the frequency and the gain chracteristic is better than the proposde circuit by Soliman, according as the rate of feedback resistors of compensated circuit changes. Voltage follower accomplishies compgnsation using the same circuit. Also, the compensation circuit to increase O-ffactor in inverting integrator is proposed.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1987.10a
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• pp.242-244
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• 1987

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.04a
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• pp.197-201
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• 1991

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.531-538
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• 2005

In the high performance Analog Information Processing Systems(AIPS), gain boosting or additional gain stage is required when the gain is not sufficient with one stage amplification. This work shows that high gain is neatly obtained by enhancing the gain using the negative resistance element. Compared to the conventional techniques, the proposed scheme enjoys full output swing, small circuit area and power consumption, and the applications to various configurations of amplifiers. The negative resistance element is placed between the differential output nodes when used in the Op-Amp. The HSPICE simulation indicates that enhancement of more than 40 dB is readily obtained in this simple configuration when the negative resistance element is implemented in the form of cross-coupled CMOS inverters.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.4
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• pp.19-24
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• 1974

An ungrounded inductance, necessary for construction of general type networks, is synthesized using two operational amplifiers and several passive elements. Through indefinite admittance matrix procedure. it is proved that the synthesized network is equivalent to an ungrounded pure inductance with a positive and a negative resistance in the parallel arms. A practical low-pass filter is made according to this synthesis method, and the resultant characteristic has been verified by means of IBM's simulation program ECAP (Electronic Circuit Analysis Program).

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.137-144
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• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.