• Journal of KIISE:Computer Systems and Theory
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• v.27 no.9
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• pp.816-823
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• 2000

상위단계 합성에서 데이터 저장을 위한 메모리 할당 문제는 중요하게 다루어지는 영역의 하나이다. 이 논문에서는, 다중포트(multiport)메모리 할당 문제에 대한 새로운 방법을 제안한다. 문제의 복잡도를 줄이기 위해, 기존의 연구들은 요약하면, 두 단계의 과정으로 이루어지고 있다. 첫 번째 단계에서는 변수들을 몇 개씩 묶어서 하나의 메모리를 형성한다. (즉 메모리 최적화 문제를 푼다.) 두 번째 단계에서는 메모리들과 기능모듈들 간의 연결선을 최적화시킨다. (즉, 연결선 최적화 문제를 푼다) 이 경우 심각한 단점은 연결선의 비용을 최소화하는 데는 한계가 있다는 것이다. 다시 말해, 연결선의 비중이 점점 중요하게 되어지는 설계 추세에서 기존의 방법은 다중포트 메모리 사용을 통해 얻을 수 있는 연결선 최소화를 극대화하는데 한계가 있음을 뜻한다. 이를 극복하기 위해, 우리는 새로운 할당 방법을 제시한다. 구체적으로 먼저, 연결선 최소화를 해결하고, 그 다음에, 메모리 최적화를 시도한다. 또한 제안한 알고리즘은 연결선 최소화 과정 동안 다음 단계에서 결정될 메모리 비용도 적절히 고려한다. 우리는 다양한 실험을 통해, 우리의 제안한 방법이 기존의 연구보다 상당히 효율적인 것임을 보인다.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.47-54
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• 2004

Up to the present, there have been many works to analyze interconnects on timing aspects, while less works have been done on power aspects. As resistance of interconnects and rise time of signals increase, power consumption associated with interconnects is ever-increasing. In case of clock trees, particularly power consumption associated with interconnects is over 30％ of total power consumption. Hence, an efficient method to compute power consumption of interconnects is necessary and in this paper we propose a simple yet accurate method to estimate dynamic power consumption of interconnects. We propose a new reduced-order model to estimate power consumption of large interconnects. Through the proposed model which is directly derived from total capacitance and resistance of interconnects, we show that the dynamic power consumption of whole interconnects can be approximated, and propose an analytical method to compute the power consumption. The results applying the proposed method to various RC networks show that average relative error is 1.86％ and maximum relative error is 9.82％ in comparison with HSPICE results.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.39 no.6
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• pp.853-858
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• 2019

One of the methods which can enhance the efficiency of railroad network is construction of interconnection branch line for several route to share one railway. In Korea, this method already has been implemented or excuted as project level. This study suggests a network design model and a solution algorithm to choice most proper site to construction it and determine the priority of branch lines which can be considered in planning level, not project level. The model is a non-linear optimization program which minimize total cost-construction cost, operating cost and passengers' travel cost. The decision variables are a binary variable to explain whether construction or not and its direction and a integer variable of the frequencies of travel routes. The solution algorithm-problem solution and route choice and also the result of implementation for example network are suggested. This result can be more advanced after application in real network and calibration of parameters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.53-59
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• 2004

This paper proposes an efficient method for computing the 3-dimensional capacitance of complex structures. The proposed method is based on applying numerical 2-dimensional capacitance extraction formula for 3-dimensional interconnect models. This method improves the extraction efficiency 952 times while compromising the accuracy within 1.8 percentage of maximal relative error, compared with the results of Fastcap program for various 3-D models. The proposed method can be used efficiently to extract electrical parameters of on/off-chip interconnects in VLSI systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.69-77
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• 2004

An efficient board-level interconnect test algorithm is proposed considering both the ground bounce effect and the delay fault detection. The proposed algorithm is capable of IEEE 1149.1 interconnect test, negative ground bounce effect prevention, and also detects delay faults as well. The number of final test pattern set is not much different with the previous method, even our method enables to detect the delay faults in addition to the abilities the previous method guarantees.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.1-9
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• 1999

Timing-level circuit analyses are used to obtain fast and accurate results, and the analysis of gate and interconnect delay is necessary to validate the correctness of circuit design. This paper proposes an efficient algorithm which simultaneously calculates the gate delay and the transition time of linearized voltage source for subsequent interconnect delay calculation. The notion of effective capacitance is used to calculate the gate delay and the transition time of linearized voltage source which considers the on-resistance of driving gate. The procedure for obtaining the gate delay and the transition time of linearized voltage source has been developed through an iterative operation using the precharacterized data of gates. While previous methods require extra information for the transition time calculation of linearized voltage sources, our method uses the derived data during the gate delay calculation process, which does not require any change in the precharacterization process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.67-75
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• 2004

This paper presents a buffer insertion method for RLC-class interconnect structured as a sin91e line or a tree. First, a closed form expression for the interconnect delay of a CMOS buffer driving single RLC line is represented. This expression has been derived by the n-th power law for deep submicrometer technology and occurs to be within 9 percentage of maximal relative error in accuracy compared with the results of HSPICE simulation for various RLC loads. This paper proposes a closed form expression based on this for the buffer insertion of single RLC lines and the buffer sizing algorithms for RLC tree interconnects to optimize path delays. The proposed buffer insertion algorithms are applied to insert buffers for several interconnect trees with a 0.25${\mu}{\textrm}{m}$ CMOS technology and the results are compared against those of HSPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.113-122
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• 2004

A new diagnosis method for FPGA interconnects is developed. The proposed method diagnoses all the fault types for FPGA interconnects. It is also applied to all the modem FPGA devices like Xilinx Virtex FPGAS. Most of all, it takes shorter time to diagnose all the faults than previous diagnosis methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.9-17
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• 2011

As semiconductor process rapidly developed, the density of chips becomes higher and the space between adjacent lines narrows smaller. This trend increases the capacitance and inductance in interconnects and the coupling-capacitance of adjacent lines grows even bigger than the self-capacitance of themselves, especially in global interconnects. Inductive and capacitive coupling observed in these phenomena may cause serious problems in signal integrity. This paper proposes a codeword generation technique using extra interconnect lines to reduce the crosstalk caused by inductive and capacitive coupling and to reduce dynamic power consumption considering probability of input data. To estimate the performance of the proposed technique, the experimental results have been obtained using FastCap, FastHenry and HSPICE, and it has been shown that the power consumption using the proposed technique has yielded approximately 15% less than the results of the previous technique.