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Dynamic Power Estimation Method of VLSI Interconnects  

박중호 (숭실대학교 컴퓨터학과)
정문성 (숭실대학교 컴퓨터학과)
김승용 (숭실대학교 컴퓨터학과)
김석윤 (숭실대학교 컴퓨터학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.2, 2004 , pp. 47-54 More about this Journal
Abstract
Up to the present, there have been many works to analyze interconnects on timing aspects, while less works have been done on power aspects. As resistance of interconnects and rise time of signals increase, power consumption associated with interconnects is ever-increasing. In case of clock trees, particularly power consumption associated with interconnects is over 30％ of total power consumption. Hence, an efficient method to compute power consumption of interconnects is necessary and in this paper we propose a simple yet accurate method to estimate dynamic power consumption of interconnects. We propose a new reduced-order model to estimate power consumption of large interconnects. Through the proposed model which is directly derived from total capacitance and resistance of interconnects, we show that the dynamic power consumption of whole interconnects can be approximated, and propose an analytical method to compute the power consumption. The results applying the proposed method to various RC networks show that average relative error is 1.86％ and maximum relative error is 9.82％ in comparison with HSPICE results.
Keywords
Power estimation; Interconnect;
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