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A Minimized Test Pattern Generation Method for Ground Bounce Effect and Delay Fault Detection  

김문준 (숭실대학교 컴퓨터학과)
이정민 (숭실대학교 컴퓨터학과)
장훈 (숭실대학교 컴퓨터학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.11, 2004 , pp. 69-77 More about this Journal
Abstract
An efficient board-level interconnect test algorithm is proposed considering both the ground bounce effect and the delay fault detection. The proposed algorithm is capable of IEEE 1149.1 interconnect test, negative ground bounce effect prevention, and also detects delay faults as well. The number of final test pattern set is not much different with the previous method, even our method enables to detect the delay faults in addition to the abilities the previous method guarantees.
Keywords
IEEE 1149.1; Interconnect Test; Ground Bounce; Delay Fault Test;
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