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A Low Power FPGA Architecture using Three-dimensional Structure  

Kim, Pan-Ki (연세대학교 프로세서연구실)
Lee, Hyoung-Pyo (연세대학교 프로세서연구실)
Kim, Hyun-Pil (연세대학교 프로세서연구실)
Jun, Ho-Yoon (연세대학교 프로세서연구실)
Lee, Yong-Surk (연세대학교 프로세서연구실)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.34, no.12, 2007 , pp. 656-664 More about this Journal
Abstract
Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.
Keywords
3D-FPGA; Low power PPGA;
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