• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.46 no.10
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• pp.876-882
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• 2018

The purpose of this research is to verify the feasibility of Plastic Ball Grid Array (PBGA), one of the most popular chip packaging types for commercial electronics, under strong random vibration occurred in satellite during launch. Experiment were performed by preparing daisy chained PCB specimen, where large size PBGA were surface mounted, and the PCB was fixed to an aluminum frame which is commonly used to install the electronics parts to satellite. Then the entire sample was fixed to vibration tester. The random vibration power spectrum density employed in the tests were composed of two steps, the acceptance level of 22.7 Grms, and qualification level of 32.1 Grms with given period of time. The test results showed no solder cracks, which provided the strong structural integrity and feasibility evidences of the PBGA packaging to aerospace electronics. Numerical analyses were also performed to calculate the solder stresses and analyze their development mechanism.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.59-70
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• 2004

SMT(Simultaneous Multi Threading) architecture uses TLP(Thread Level Parallelism) and increases processor throughput, such that issue slots can be filled with instructions from multiple independent threads. Having multiple ready threads reduces the probability that a functional unit is left idle, which increases processor efficiency. To utilize those advantages for the SMT processors, the issue unit must control the flow of instructions from different threads and not create conflicts among those instructions, which make the SMT issue logic extremely complex. Therefore, our SMT architecture, which is modeled in this paper, uses an in-order-issue and completion scheme, and therefore, can use a simple issue mechanism with a scoreboard already instead of using register renaming or a reorder buffer. However, an SMT scoreboarding mechanism is still more complex and costlier than that of a single threaded conventional processor. This paper proposes an optimal implementation of a scoreboarding mechanism for an ARM-based SMT architecture.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.449-449
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• 2013

최근 반도체 소자의 집적회로는 점점 복잡해지고 있는 반면, 소자의 크기는 작아지고 있으며 그로 인해 패드의 크기가 작아지고 패드사이의 간격 또한 협소해지고 있다. 따라서 웨이퍼 단계에서 제조된 집적회로의 불량여부를 판단하기위한 검사 장비인 프로브카드(Probe Card)의 높은 집적도가 요구되고 있다. 하지만 기존의 MEMS 공법으로 제작되는 프로브 빔은 복잡한 제조 공정과 높은 생산비용, 낮은 집적도의 문제점을 가지고 있다. 본 연구에서는 이러한 문제점을 해결하기 위하여 간단한 제조 공정과 낮은 생산비용, 높은 집적도를 가지는 프로브 빔을 개발하기 위하여 절연절단 방식으로 BeCu (Beryllium-Copper) 프로브 빔을 제작하였다. 낮은 소비 전력으로 우수한 프로브 빔 어레이를 제작하기 위해서 가장 고려해야할 대상은 프로브 빔의 재료와 구조(형상)이다. 절연전단 방식으로 프로브 빔을 형성할 때 요구되는 Fusing current는 프로브 빔의 구조(형상)에 크게 영향을 받는다. 낮은 Fusing current는 소비 전력을 줄여주고, 절연절단으로 형성되는 프로브 빔의 단면(끝)을 날카롭게 하여 프로브 빔과 집적회로의 패드 간의 접촉 저항을 감소시킨다. 프로브 빔의 제작은 BeCu 박판을 빔 형태로 식각하여 제작하였으며, 실리콘 비아 홀(Via hole) 구조의 기판위에 정렬하여 soldering 공정을 통해 실리콘 기판과 BeCu 박판을 접합시켰다. 접합된 프로브 빔의 끝부분을 들어 올린 상태로 전류를 인가하여 stress free 상태로 만들어 내부 응력을 제거하였으며, BeCu 박판에 fusing current를 인가하여 BeCu 박판 프레임으로부터 제거를 하였다. 제작된 프로브 빔의 길이는 1.7 mm, 폭은 $50{\mu}m$, 두께는 $15{\mu}m$, 절단부의 단면적은 1$50{\mu}m^2$로 제작되었다. 그리고 프로브 빔의 절단부의 길이는 $50{\mu}m$ 부터 $90{\mu}m$까지 $10{\mu}m$ 증가시켜 제작되었다. 이후에 절연절단 공정에 요구되는 Fusing current를 측정하였고, 절연절단 후의 절단면의 형상을 SEM (Scanning Electron Microscope)장비를 통하여 확인하였다. 절단부의 길이가 $50{\mu}m$일 때 5.98A의 fusing current를 얻었으며, 절연절단 후 절단부 상태 또한 가장 우수했다. 본 연구에서 제안된 프로브 빔 제작 방법은 프로브카드 및 테스트 소켓(Test socket) 생산에 응용이 가능하리라 기대한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.503-509
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• 2007

Low-power motion estimation is required for video coding in portable information devices. In this paper, we propose a low-power motion estimation algorithm and 1-D systolic may VLSI architecture using full search block matching algorithm (FSBMA). Main power dissipation sources of FSBMA are complex computations and frequent memory accesses for data in the search area. In the proposed algorithm, memory accesses and computations are reduced by using 1D PE (processing array) array architecture performing motion estimation of two neighboring blocks in parallel and by skipping unnecessary computations during motion estimation. The VLSI implementation results of the algorithm show that the proposed VLSI architecture can save 9.3% power dissipation and can operate two times faster than an existing low-power motion estimator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1141-1146
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• 2004

The antenna array for receiving satellite broadcasting of Koreasat III is proposed. A cavity-backed slot antenna array is proposed to reduce feed line loss, increase the radiation efficiency, and make the feed network simple. A sub-array consists of $2{\times}4$ slot elements backed by a single cavity. By proper choice of dimensions it is shown that the proposed antenna has characteristics of the high radiation efficiency and the broad frequency bandwidth. Antenna characteristics for the array antenna with 256 elements are measured in Ku-band. A single cavity backed-sub-array has the gain of 18 dEi. The gam of the total antenna array(256 elements) is Over 33 dEi.

• Journal of IKEEE
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• v.25 no.4
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• pp.634-643
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• 2021

In this paper, an FPGA-based acceleration scheme of range Doppler algorithm (RDA) is proposed for the real time synthetic aperture radar (SAR) imaging. Hardware architectures of matched filter based on systolic array architecture and a high speed sinc interpolator to compensate range cell migration (RCM) are presented. In addition, the proposed hardware was implemented and accelerated on Xilinx Alveo FPGA. Experimental results for 4096×4096-size SAR imaging showed that FPGA-based implementation achieves 2 times acceleration compared to GPU-based design. It was also confirmed the proposed design can be implemented with 60,247 CLB LUTs, 103,728 CLB registers, 20 block RAM tiles and 592 DPSs at the operating frequency of 312 MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.3
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• pp.217-223
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• 2009

Recently, the development of the various network method can generate serious social problems. So, it is highly required to control security of network. These problems related security will be developed and keep up to confront with anti-security field such as hacking, cracking. The way to preserve security from hacker or cracker without developing new cryptographic algorithm is keeping the state of anti-cryptanalysis in a prescribed time by means of extending key-length. In this paper, the proposed montgomery multiplication structured unit array method in carry generated part and variable length multiplication for eliminating bottle neck effect with the RSA cryptosystem. Therefore, this proposed montgomery multiplier enforce the real time processing and prevent outer cracking.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.14-24
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• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.90-96
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• 2014

This paper presents a practical linearization technique for a wide-band bang-bang digital phase locked-loop(BBDPLL) by selecting optimal loop gains. In this paper, limitation of the theoretical design method for BBDPLL is explained, and introduced how to implement practical BBDPLLs with CMOS process. In the proposed BBDPLL, the limited cycle noise is removed by reducing the proportional gain while increasing the integer array and dither gain. Comparing to the conventional BBDPLL, the proposed one shows a small area, low power, linear characteristic. Moreover, the proposed design technique can control a loop bandwidth of the BBDPLL. Performance of the proposed BBDPLL is verified using CppSim simulator.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.180-181
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• 2009

$(Ba_{0.6},Sr_{0.3}Ca_{0.1})TiO_3$ powders, which were prepared by sol-gel method using a solution of Ba-acetate, Sr-acetate and Ca-acetate and Ti iso-propoxide, $(Ba_{0.6},Sr_{0.3}Ca_{0.1})TiO_3$ array thick films doped with 0.1 mol% $MnCO_3$ and $Yb_2O_3$ (0.1~0.7 mol%) were fabricated by the screen printing method on the alumina substrate. And the structural and electrical properties as a function of $Yb_2O_3$ amount were investigated. The thickness of all (Ba,Sr,Ca)$TiO_3$ thick films was approximately 60mm. The Curie temperature of doped with 0.1 mol% $Yb_2O_3$ specimen was $45^{\circ}C$, and the dielectric constant and at this temperature was 1062.