Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Parallel Testing Circuits with Versatile Data Patterns for SOP Image SRAM Buffer

SOP Image SRAM Buffer용 다양한 데이터 패턴 병렬 테스트 회로

  • Jeong, Kyu-Ho (Samsung Electronics, Device Solution) ;
  • You, Jae-Hee (School of Electronic & Electrical Eng., Hongik University)
  • Published : 2009.09.25
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Abstract

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

System on panel 프레임 버퍼를 위한 메모리 셀 어레이와 주변회로가 설계되었다. 또한, system on panel 공정의 낮은 yield를 극복하기 위해, 블럭 단위의 parallel test 방안이 제안되었다. 기존의 메모리 테스트 보다 빠르게 fault detection이 가능하며, 다양한 embedded memory나 일반 SRAM 테스트 분야에도 적용 가능하다. 또한 기존의 다양한 test vector pattern이 그대로 적용될 수 있어 fault coverage가 높고, 최근의 추세인 hierarchical bit line과 divided word line 구조에도 적용될 수 있다.

Keywords

References

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