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VLSI Implementation of Low-Power Motion Estimation Using Reduced Memory Accesses and Computations  

Moon, Ji-Kyung (경희대학교 전자전파공학과)
Kim, Nam-Sub (한림대학교 전자공학과)
Kim, Jin-Sang (경희대학교 전자전파공학과)
Cho, Won-Kyung (경희대학교 전자전파공학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.32, no.5A, 2007 , pp. 503-509 More about this Journal
Abstract
Low-power motion estimation is required for video coding in portable information devices. In this paper, we propose a low-power motion estimation algorithm and 1-D systolic may VLSI architecture using full search block matching algorithm (FSBMA). Main power dissipation sources of FSBMA are complex computations and frequent memory accesses for data in the search area. In the proposed algorithm, memory accesses and computations are reduced by using 1D PE (processing array) array architecture performing motion estimation of two neighboring blocks in parallel and by skipping unnecessary computations during motion estimation. The VLSI implementation results of the algorithm show that the proposed VLSI architecture can save 9.3% power dissipation and can operate two times faster than an existing low-power motion estimator.
Keywords
VLSI;
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