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http://dx.doi.org/10.5573/ieie.2014.51.1.090

Linearization Technique for Bang-Bang Digital Phase Locked-Loop by Optimal Loop Gain Control  

Hong, Jong-Phil (School of Electrical Engineering, Chungbuk National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.1, 2014 , pp. 90-96 More about this Journal
Abstract
This paper presents a practical linearization technique for a wide-band bang-bang digital phase locked-loop(BBDPLL) by selecting optimal loop gains. In this paper, limitation of the theoretical design method for BBDPLL is explained, and introduced how to implement practical BBDPLLs with CMOS process. In the proposed BBDPLL, the limited cycle noise is removed by reducing the proportional gain while increasing the integer array and dither gain. Comparing to the conventional BBDPLL, the proposed one shows a small area, low power, linear characteristic. Moreover, the proposed design technique can control a loop bandwidth of the BBDPLL. Performance of the proposed BBDPLL is verified using CppSim simulator.
Keywords
bang-bang phase and frequency detector; digital phase-locked loop; jitter; limited cycle noise; nonlinear;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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