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Implementation of a Scoreboard Array and a Port Arbiter for In-order SMT Processors  

Heo, Chang-Yong (Digital Media Business, Samsung Electronics)
Hong, In-Pyo (Processor Laboratory, Dept. of Electrical and Electronic Engineering, Yonsei University)
Lee, Yong-Surk (Processor Laboratory, Dept. of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.6, 2004 , pp. 59-70 More about this Journal
Abstract
SMT(Simultaneous Multi Threading) architecture uses TLP(Thread Level Parallelism) and increases processor throughput, such that issue slots can be filled with instructions from multiple independent threads. Having multiple ready threads reduces the probability that a functional unit is left idle, which increases processor efficiency. To utilize those advantages for the SMT processors, the issue unit must control the flow of instructions from different threads and not create conflicts among those instructions, which make the SMT issue logic extremely complex. Therefore, our SMT architecture, which is modeled in this paper, uses an in-order-issue and completion scheme, and therefore, can use a simple issue mechanism with a scoreboard already instead of using register renaming or a reorder buffer. However, an SMT scoreboarding mechanism is still more complex and costlier than that of a single threaded conventional processor. This paper proposes an optimal implementation of a scoreboarding mechanism for an ARM-based SMT architecture.
Keywords
SMT; TLP; scoreboard; thread; issue;
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1 Hily, S., Seznec, A., 'Out-of-order execution may not be cost-effective on processors featuring simultaneous multi-threading', in Proc. of High-performance computer architecture, fifth international symposium, pp64-67, 9-13 jan 1999
2 Robert J. Baron, Lee Higbie, 'Computer Architecture', Addison-wesley publishing company, 1992
3 John L. Hennessy, David A. Patterson, 'Computer Organization and Design', Morgan Kaufmann, Publishers, Inc. 1998
4 Toyohiko Yoshida, Masahito Matsuo, Tatsuya Ueda and Yuichi Saito, 'A Strategy for Avoiding Pipeline Interlock Delays in a Microprocessor', in Proc. of Computer Design:VLSI in Computers and Processors, ICCD '90., pp.14_19, 17-19 Sep 1990   DOI
5 R. Balasubramonian, S. Dwarkadas, D.H. Albonesi, 'Reducing the Complexity of the Register File in Dynamic Superscalar Processors', in Proc. of 34th annual ACM/ IEEE international symposium on Micro- architecture, pp. 237-248, Texas, 2001
6 ARM Architecture Reference Manual, Part A. CPU Architecture, 1996
7 Dean M.Tullsen, Susan J. Eggers, Henry M. Levy, 'Simultaneous Multithreading Maximizing On-Chip Parallelism', in Proc. of 22nd Annual International Symposium on Computer Architecture, pp. 392-403, 22-24, Jun 1995
8 Sorin Cotofana, Stamatis Vassiliadis, 'On the Design Complexity of the Issue Logic of Super scalar Machines', in Proc. of 24th Euro- micro Conference, pp. 277-284, 25-27, Aug. 1998
9 Dezso Sima, Terence Fountain, Peter Kacsuk, 'Advanced computer architectures', Addison-Wesley, 1998
10 문병인, '순차적 SMT 구조 및 그룹화 방안에 관한 연구', 연세대학교 대학원 전기전자공학과, 공학박사 학위논문, 2002년 12월
11 Roger Espasa, Mateo Valero, James E. Smith, 'Out-of-order vector architectures', in Proc. of 30th annual ACM/IEEE international symposium on Microarchitecture, pp. 160-170, 1997
12 Gurindar S. Sohi, Scott E. Breach, T.N. Vijaykumar, 'Multiscalar processors', in Proc. of 22nd annual international symposium on Computer architecture, pp. 414-425, S. Margherita Ligure, Italy 1995