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Parallel Testing Circuits with Versatile Data Patterns for SOP Image SRAM Buffer  

Jeong, Kyu-Ho (Samsung Electronics, Device Solution)
You, Jae-Hee (School of Electronic & Electrical Eng., Hongik University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.9, 2009 , pp. 14-24 More about this Journal
Abstract
Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.
Keywords
System on Panel; Frame buffer; Embedded memory; Parallel test; Redundancy;
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  • Reference
1 Seung-yong Lee et al., IMID 2007 Digest, "Design Considerations on the Partition of SOP , CMOS and PCB", Aug. 2007
2 B. Lee, et al., "A CPU on a glass substrate using CG-silicon TFTs," IEEE ISSCC 2003, vol. 1, pp.164-165, 2003
3 H. Ebihara et al., "A Flexible 16kb SRAM based on Low-Temperature Poly-Silicon (LTPS)", Society of Information Display, SID 06 Digest pp. 339-342, 2006
4 S. Kang et al., "Memory Test", Dae-young-sa, 2001
5 T. Tseng et. al., "A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs," IEEE International Test Conference, Oct. 2008   DOI
6 R. C. Aitken, " A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories," Proc. of International Test Conference, 2004   DOI
7 M. Kinugawa et al., "TFT(Thin Film Transistor) Cell Technology for 4M Bit and More High Density SRAMs", Symposium on VLSI technology, pp. 23-24, 1990   DOI
8 L. Denq et. al, "A parallel built-in diagnostic scheme for multiple embedded memories," International Workshop on Memory Technology, Design and Testing, Aug. 2004   DOI
9 S. Hamdioui et. al, "The state-of-art and future trends in testing embedded memones," International Workshop on Memory Technology, Design and Testing, 2004
10 http://www.samsung.com/global/business
11 H. Haga et al., "A 51O-Kb SOG-DRAM for Frame-Memory-Integrated Displays", Society of Information Display, SID Digest pp. 1100-1109, 2005
12 A Karandikar and K K Parhi, "Low Power SRAM Design using Hierarchical Divided Bit-Line Approach", International Conference on VLSI in Computers and Processors, IceD '98 Proceedings, 5-7 pp. 82 - 88, Oct. 1998   DOI
13 Bo-Sung Kim et al., "Low Power 260k Color VGA TFT LCD One-chip Driver le", ISSCS 2007, July 2007
14 J. C. Yeh et. al, " A Systematic Approach to Reducing Semiconductor Memory Test Time in Mass Production", Proc. of the 2005 IEEE International Workshop on Memory Technology, Design and Testing, 2005   DOI
15 O. Spang, "A Sophisticated Memory Test Engine for LCD Display Drivers," Europe Conference & Exhibition in Design, Automation & Test, April 2007
16 T. Matsuo, et al., "CG Silicon Technology and Development of System on Panel," SID pp. 856-859, 2004
17 T. Th:eda, et al., "Full-Functional System Liquid Crystal Display Using CG-Silicon Technology," SID pp. 860-863, 2004
18 A. J. Van de goor, Testing Semiconductor Memories - Theroy and Practice, John Wlley & Sons, UK, 1991