• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1619-1626
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• 2021

Unlike traditional delta-sigma analog-to-digital converters, incremental analog-to-digital converters enable 1:1 mapping of input and output through a reset operation, which can be used very easily for multiplexing. Incremental analog-to-digital converters also allow for simpler digital filter designs compared to traditional delta-sigma converters. Therefore, starting with analysis in the time domain of the delayed integrator and non-delayed integrator, which are the basic blocks of analog-to-digital converter design, the design equations of a second-order input feed-forward, extended counting, 2+1 MASH (Multi-stAge-noise-SHaping), 2+2 MASH incremental analog-to-digital converter are derived in this paper. This allows not only prediction of the performance of the incremental analog-to-digital converter before design, but also the design of a digital filter suitable for each analog-to-digital converter. In addition, extended counting and MASH design techniques were proposed to improve the accuracy of analog-to-digital converters.

• Journal of IKEEE
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• v.17 no.3
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• pp.234-240
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• 2013

This paper presents an incremental delta-sigma analog-to-digital converter (ADC) for a single-electrode capacitive touch sensor. The second-order cascade of integrators with distributed feedback (CIFB) delta-sigma modulator with 1-bit quantization was fabricated by a $0.18-{\mu}m$ CMOS process. In order to achieve a wide input range in this incremental delta-sigma analog-to-digital converter, the shielding signal and the digitally controlled offset capacitors are used in front of a converter. This circuit operated at a supply voltage of 2.6 V to 3.7 V, and is suitable for single-electrode capacitive touch sensor for ${\pm}10-pF$ input range with sub-fF resolution.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• Journal of IKEEE
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• v.22 no.3
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• pp.786-792
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• 2018

A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.39-46
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• 2005

A DC-DC converter with digital controller is realized. the digital controller has several advantages such as robustness, fast design time, and high flexibility. however, since the DC-DC output voltage is analog, an analog-to-digital conversion scheme is always essential in all digital controllers. A simple and efficient delta-sigma modulator is used as a conversion scheme in out implementation. The measurement results show good voltage regulation

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1887-1894
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• 2010

This paper proposes a new switched-capacitor sigma-delta modulator for automotive radars. Developed modulator is used to perform high-resolution analog-to-digital conversion (ADC) of high frequency band signal in a radar system. It has supply voltage of 2.7V, and has body-effect compensated switch configuration with low voltage and low distortion. The modulator has been implemented in a $0.25{\mu}m$ double-poly and triple-metal standard CMOS process, and it has die area of $1.9{\times}1.5mm^{2}$. It showed better total harmonic distortion of 20dB than the conventional bootstrapped circuit at the supply voltage of 2.7V.